5nm Vs. 3nm


Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

Week In Review: Manufacturing, Test


Trade wars In recent testimony before a U.S. government panel considering tariffs on $300 billion worth of Chinese goods, SEMI called for the removal of about 30 tariff lines. These items are central to the semiconductor manufacturing process. “SEMI asserts that these tariffs will harm not only companies operating in the U.S., but other companies as well in the semiconductor supply chain... » read more

Advanced Process Control


David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures. » read more

Factoring Reliability Into Chip Manufacturing


Making chips that can last two decades is possible, even if it's developed at advanced process nodes and is subject to extreme environmental conditions, such as under the hood of a car or on top of a light pole. But doing that at the same price point as chips that go into consumer electronics, which are designed to last two to four years, is a massively complex challenge. Until a couple of y... » read more

Falling Chip Forecasts


It’s time to take a pulse of the semiconductor market amid the memory downturn and trade frictions with China. For some time, the DRAM and NAND markets have been hit hard with falling prices and oversupply. Then, the Trump administration last year slapped tariffs on Chinese goods. China retaliated. And the trade war rages on between the U.S. and China. More recently, the U.S. Department... » read more

Material Solutions For FOWLP Die Shift And Wafer Warpage


By Shelly Fowler Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower-profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-via... » read more

What’s Next In Advanced Packaging


Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

New Applications Call For New Memory Types


The semiconductor industry is on the verge of a transformative computing era driven by Big Data, Artificial Intelligence (AI) and the Internet of Things (IoT). However, achieving the improvements in computing performance and efficiency needed for new AI and IoT applications represent some of the biggest technology challenges the industry has faced. Among the most critical requirements is del... » read more

Automotive Semiconductors Boost MCU, Analog Markets


Auto sales are expected to experience a slowdown in 2019, and even with the continued increase in electronics per vehicle, automotive semiconductor sales are also expected to experience a slowdown. Similar to prior years, 2019/2020 car models will include more automotive semiconductor devices to provide higher degrees of safety, comfort and convenience, driver assist capabilities, in-cabin ente... » read more

Possible Uses Narrow For Negative Capacitance FETs


The discovery of a ferroelectric phase in hafnium dioxide (HfO2) has sparked significant interest in opportunities for integration of ferroelectric transistors and memories with conventional CMOS devices. Demonstrations of “negative capacitance” behavior in particular suggest these devices might evade the 60 mV/decade limit on subthreshold swing, thereby improving transistor efficiency. ... » read more

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