Are Larger Reticle Sizes On The Horizon?


Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits or a wholesale change to larger masks. Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6x6-inch to 6x11-inch masks that would eliminate stitching, but it... » read more

2024 Corporate Responsibility Report


Amkor recognizes the need for transparent reporting, and we have been publishing annual reports to facilitate the disclosure of comparable, consistent, and reliable information about our initiatives and progress for our stakeholders. Last year, we verified our targets to achieve net-zero greenhouse gas emissions by 2050, including near-term targets, with the Science Based Targets initiative ... » read more

Photomask Changes And Challenges At Mature And Advanced Nodes


Experts at the Table: Semiconductor Engineering sat down to discuss the current state and future direction of mask-making, with Harry Levinson, principal lithographer at HJL Lithography; Aki Fujimura, CEO of D2S; Ezequiel Russell, senior director of mask technology at Micron; and Christopher Progler, executive vice president and CTO at Photronics. What follows are excerpts of that conversation.... » read more

Big Changes In Medical Electronics


Medical devices are becoming more capable, more complicated, and more deployable in the field rather than in a hospital or a doctor's office. But getting these purpose-built devices into the hands of consumers requires a whole bunch of new challenges, from safeguarding fragile on-board chemistries that can be destroyed by existing chip manufacturing and packaging processes to ensuring the mater... » read more

Photomask Japan 2025: A Strong Signal For The Future Of Our Industry


Photomask Japan (PMJ) 2025 was, without a doubt, the most exciting edition I’ve attended in recent years. From a surge in attendance to a packed agenda full of technical depth and forward-looking insights, this year’s event reflected the growing momentum and innovation across the photomask and eBeam ecosystem. Let’s start with the numbers—624 attendees. That’s a significant jump fr... » read more

Co-Packaged Optics Reaches Power Efficiency Tipping Point


Commercialization has started for network switches based on co-packaged optics (CPO), which are capable of routing signals at terabits per second speeds, but manufacturing challenges remain regarding fiber-to-photonic IC alignment, thermal mitigation, and optical testing strategies. By moving the optical-to-electronic data conversion as close as possible to the GPU/ASIC switch in data center... » read more

Maximizing Signal Integrity: Fine-Tuning Via Impedance In HDFO Architectures


The most different aspect between a normal lamination structure and High-Density Fan-out (HDFO) is the routing scale. That aspect is also the challenge and focus of this study. At an HDFO scale, most of the electrical properties cannot be measured by instruments. Therefore, this study uses the indirect method to determine the impedance information of the via and match the impedance. Since the v... » read more

Revolutionizing Semiconductor Development With GPU-Enhanced Atomistic Modeling


There are many challenges in the development of a modern semiconductor chip, from front-end architecture simulation to final signoff. Volume manufacturing has its own set of challenges, while silicon lifecycle management (SLM) extends into field deployment and aging concerns. Underlying this entire development flow, however, lie the materials used to build the actual chips. Guiding the explorat... » read more

Cooling Chips Still A Top Challenge


Increasing levels of semiconductor integration means more work needs to be done in smaller spaces, which in turn generates more heat that needs to be dissipated. Managing heat dissipation in advanced node dies and in multi-die assemblies is critical to their functionality and their longevity. And while much of the focus has been on improving power efficiency, which reduces the rate of power ... » read more

Mask Complexity, Cost, And Change


Experts at the Table: As leading-edge lithography nodes push further into EUV and beyond, mask-making has become one of the most critical and costly aspects of semiconductor manufacturing. At the same time, non-EUV applications are stretching the lifetime of older tools and processes, challenging the industry to find new solutions for both ends of the spectrum. Semiconductor Engineering sat dow... » read more

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