category: Manufacturing, Packaging and Materials

category: Auto, Security & Edge AI

Laser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching
By Timothy Yang - 22 May, 2025 - Comments: 2

Extreme ultraviolet (EUV) lithography exposed resist patterns can exhibit excessive line edge roughness (LER) and line width roughness (LWR) due to random or shot noise. Increasing the EUV exposure dose can reduce LER/LWR, but it also decreases wafer throughput, which is highly undesirable given the EUV tool’s high operating costs. Ion beam etching (IBE) can directionally etch away roug... » read more

Molybdenum: Transforming Semiconductor Manufacturing For Next-Generation Technologies
By Lam Research - 22 May, 2025 - Comments: 0

One trillion semiconductors produced in a single year. A digital foundation powering AI's explosive growth. The next frontier requires chips that are smaller, faster, and exponentially more powerful. A new white paper from Counterpoint Research  reveals how advanced metallization—specifically molybdenum—is becoming a critical enabler for semiconductor manufacturing in this new era. Th... » read more

Energy-Efficient Computing Systems For Sustainable AI
By Pushkar Apte - 22 May, 2025 - Comments: 0

As artificial intelligence (AI) proliferates rapidly, AI models and datasets are also growing rapidly in size. This growth far outpaces performance improvement in hardware systems, and is increasing AI’s energy consumption unsustainably. To address these challenges and explore collaborative solutions, SEMI’s Smart Data-AI Initiative – as part of its Future of Computing focus – r... » read more

New Package Solutions for Automotive Optical Sensors
By Amkor - 22 May, 2025 - Comments: 0

This article introduces the development of a new optical ball grid array (OBGA) packaging platform designed for automotive applications, with a focus on platform development and compliance with the Automotive Electronics Council (AEC) AEC-Q100 Grade 2 reliability standard. The proposed packaging solution extends beyond traditional cavity OBGA packages, which have been primarily utilized for mic... » read more

Advanced Packaging Depends On Materials And Co-Design
By Katherine Derbyshire - 22 May, 2025 - Comments: 0

Multi-die assemblies offer significant opportunities to boost performance and reduce power, but these complex packages also introduce a number of new challenges, including die-to-RDL misalignment, evolving warpage profiles, and CTE mismatch. Heterogeneous integration — an umbrella term that covers many different applications and packaging requirements — holds the potential to combine com... » read more

Three-Way Race To 3D-ICs
By Ed Sperling - 05 May, 2025 - Comments: 1

Intel Foundry, TSMC, and Samsung Foundry are scrambling to deliver all the foundational components of full 3D-ICs, which collectively will deliver orders of magnitude improvements in performance with minimal power sometime within the next few years. Much attention has been focused on process node advances, but a successful 3D-IC implementation is much more complex and comprehensive than just... » read more

Co-Design Optimization For PI/SI When Considering Thermal Performance
By Peater Wu - 21 Apr, 2025 - Comments: 0

When applications become more complex, higher data rates or high frequencies are required. However, with increasing functions, more power dissipation will be generated. Furthermore, temperature is proportional to power dissipation, so electrical performance will also depend on thermal conditions. To determine how temperature impacts power integrity/signal integrity (PI/SI), electrical simulatio... » read more

The Other Side Of The Wafer: Transistor Channel Stress In Backside Power Delivery Networks
By Sam Sarkar - 17 Apr, 2025 - Comments: 0

As transistor scaling has moved to the angstrom era (18A, 14A, etc.), the issues of interconnect resistance (IR), IR drop, and power loss are becoming more severe. Traditionally, signal lines and power lines are fabricated on the same side of the wafer as the active device. But fabricating everything on one side of the wafer can create a shortage of space and resources at the interconnect la... » read more

TCAD For GPUs And GPUs For TCAD
By Shela Aboud - 17 Apr, 2025 - Comments: 0

It is well known that many steps in chip development become exponentially harder as feature sizes shrink and instance counts balloon. Billions of transistors are now commonplace, and wafer-scale devices with trillions are on the horizon. Such massive chips put pressure on every electronic design automation (EDA) tool in the development flow, from front-end architectural modeling to signoff and ... » read more

Can Chiplets Serve Cost-Conscious Apps?
By Bryon Moyer - 17 Apr, 2025 - Comments: 0

Chiplets are emerging as a significant new phase in the evolution of the semiconductor market, providing a way to continue scaling performance well beyond the size limitations of a reticle. But that improvement comes with a high price tag and a lot more complexity, which so far has limited adoption. One of the main reasons for the cost increase is the need for advanced packaging when employi... » read more

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