Week In Review: Auto, Security, Pervasive Computing


Pervasive computing Swedish-based Ericsson is selling its IoT business platform to Aeris for an undisclosed amount. Ericsson will transfer its IoT Accelerator and Connected Vehicle Cloud businesses and assets to Aeris, a company that focuses on industrial, automotive, and medical IoT networks. The complexity and fragmentation of the IoT space requires more custom and hands on maintenance. Acco... » read more

Blog Review: Dec. 7


Siemens EDA's Harry Foster looks at the continual maturing of FPGA functional verification processes through increasing adoption of various simulation-based and formal verification techniques. Synopsys' Stewart Williams introduces the Scalable Open Architecture for Embedded Edge (SOAFEE) project and how it can make automotive software development, testing, virtual prototyping, and validation... » read more

Week In Review: Semiconductor Manufacturing, Test


With the European Council’s adoption of its negotiating mandate for the European Chips Act, member states and the Czech Presidency of the Council have reached a critical milestone in supporting Europe’s efforts to advance manufacturing and supply of critical components, while bolstering R&D capacities for development of next-generation semiconductor innovations, according to SEMI. Ch... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, Mobility The U.S. space agency NASA entered a $57.2 million contract with ICON to develop technology to build roads on the moon. ICON, a Texas-based 3D printing construction company, has been working with NASA and the U.S. Air Force on construction technologies that can use local materials to build infrastructure on Mars. NASA is working on advanced 3D printing construction systems... » read more

Week In Review: Design, Low Power


Tools and IP Renesas released a family of configurable clock generators with an internal crystal oscillator for PCIe and networking applications in high-end computing, wired infrastructure and data center equipment. “Timing needs can vary greatly between different applications and equipment, and often change during a product design cycle,” said Zaher Baidas, Vice President of the Timing Pr... » read more

Blog Review: Nov. 30


Cadence's Sangeeta Soni explores how the configuration space for CXL 1.1 and CXL 2.0 varies and discusses newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow. Siemens EDA's Harry Foster continues examining trends in FPGA verification effort by looking at where both design and verification engineers spend their time. Synopsys... » read more

Blog Review: Nov. 23


Siemens EDA's Harry Foster looks at multiple data points to get a sense of effort spent in FPGA verification and increasing demand for FPGA verification engineers. Synopsys' Rimpy Chugh, Himanshu Kathuria, and Rohit Kumar Ohlayan argue that the quality of the design and testbench code is critical to a project’s success and that linting offers a comprehensive checking process for teams to s... » read more

Week In Review: Semiconductor Manufacturing, Test


Chinese memory chip maker YMTC and dozens of other Chinese entities are "at risk" of being added to a trade blacklist as soon as Dec. 6, a U.S. Commerce Department official said in prepared remarks seen by Reuters. SMIC co-CEO Zhao Haijun said on an earnings call that recent export controls from the United States will have an "adverse impact" on the company's production. The U.K. has rule... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Infineon has a non-binding Memorandum of Understanding to supply automaker Stellantis with CoolSiC “bare die” chips by reserving manufacturing capacity in the second half of the decade to the direct Tier 1 suppliers of Stellantis. CoolSiCs are Infineon’s silicon carbide (SiC) semiconductors. Stellantis will acquire aiMotive, a startup specializing in AI and autono... » read more

Week In Review: Design, Low Power


Tools and IP Cadence announced that its IP for GDDR6 is now silicon-proven for TSMC’s N5 process technology. The IP consists of Cadence PHY,  controller design IP, and verification IP (VIP), and is targeted for very high-bandwidth memory applications. “The improved PHY and controller design IP for GDDR6 with DRAM data rates at 22Gbps in the TSMC N5 process is the fastest of the GDDR6 fami... » read more

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