Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL


High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this code to RTL, which can be input to the traditional RTL downstream flow (RTL/GDS). Formally checking generated RTL can be difficult to analyze, as errors cannot be correlated to the HLS source code. ... » read more

Is End-To-End Security Possible?


Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

Automotive Outlook: 2026


The automotive industry stands at a crossroads entering 2026, facing a complex interplay of global tariffs, evolving electric vehicle (EV) dynamics, and the infusion of AI into just about everything. As manufacturers and suppliers navigate recent financing shifts and regulatory changes, they also must address consumer concerns over EV affordability and range, OEM concerns over when to develo... » read more

Security Threats Converge On IoT, Industrial ICs, Physical AI


Devices in a broad range of edge AI applications are increasingly at risk of hacking or tampering, with the stakes varying greatly depending on how much the device can impact and interact with human life. Design methods and protection techniques must now be included up front in the design cycle for optimal protection of consumers and companies as the quantum threat looms. In today’s factor... » read more

3D-IC Success Stories: Faster Bandwidth, Lower Power, On-Time Tapeouts


As scaling at advanced nodes becomes increasingly constrained by cost, yield, and power density, semiconductor innovation is shifting decisively toward 3D-IC technologies, chiplets, and heterogeneous integration. Across AI infrastructure, cloud computing, automotive electronics, and high-performance systems, design teams are moving beyond monolithic SoCs to unlock new levels of performance, e... » read more

Five Tips To Avoid Security Errors In Product Development


Riscure, now part of Keysight, has been helping chip vendors and device manufacturers improve the security of their products for years. The security scenario has changed a lot over time. The attacker profile evolved from individuals motivated by curiosity, with very limited resources and attack potential, to well-funded and organized adversaries with malicious motivations and the capacity to ex... » read more

The Evolution Of Hardware Root Of Trust Security IP


Navigate hardware-based security for semiconductors with this white paper about tRoot Hardware Secure Modules (HSMs). This paper provides security solutions for protecting digital assets in an increasingly interconnected world. Key Takeaways: Understand why robust security measures are needed for AI, IoT, and high-performance computing. Discover tRoot HSMs features, including secure ... » read more

Topology Selection For Bidirectional Energy Flow Applications Using WBG Devices


The paper provides an overview of the topology for bidirectional converters and discusses their different usage. Bidirectional energy flow applications are usually found in energy storage systems, battery systems, and can be categorized as grid-connected and DC-DC-connected. In grid-connected applications, two power conversion stages, which are power factor corrector (PFC) rectifier/inverter an... » read more

Formal Verification Of Synthesizable C++/SystemC Designs


Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens offers several apps to verify and clean C++ HLS code before running HLS and then check the equivalency between C++ and RTL. High-level synthesis (HLS) is a design flow in which design intent is des... » read more

AI Workloads at the Edge: Ensuring Performance, Privacy, and Security


Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss why some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president a... » read more

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