Blog Review: Jan. 6


In a video, Synopsys' Tim Mackey and Laurie Carr discuss the most substantial threats to today’s IoT devices and what considerations IoT manufacturers need to keep in mind as they release new products, plus the role governments should play in IoT regulation. Cadence's Paul McLellan explains the recent breach caused by a hacked update of SolarWinds' network management software and what expe... » read more

The Lost Art Of Processor Verification


As we celebrate over 50 years of microprocessors, the industry has embraced every generation of silicon process technology with architectural innovation plus new design methods that have supported innovations in almost every market segment. The interest around RISC-V is opening up increased activity around new approaches to optimize designs for the next generation of devices across multiple mar... » read more

Week In Review: Design, Low Power


The United States Army Research Laboratory is acquiring two new supercomputers, nicknamed Jean and Jay after computing pioneers Jean Jennings Bartik and Kathleen “Kay” McNulty Mauchly, according to an article in NextGov. The two systems are Liqid Computing platforms containing 48 core Intel XEON (Cascade Lake Advanced Performance) processors integrated with the largest solid state file syst... » read more

Top Tech Videos Of 2020


2020 shaped up to be a year of major upheaval, emerging markets and even increased demand in certain sectors. So it's not surprising that videos focusing on AI, balancing power and performance, designing and manufacturing at advanced nodes, advanced packaging, and automotive-related subjects were the most popular. Of the 68 videos published this year, the following were the most viewed in ea... » read more

Blog Review: Dec. 30


Cadence's Paul McLellan considers what the next ten years will look like for the RISC-V ISA with an expanding software ecosystem and increasing number of commercial and open cores available. Siemens EDA's Harry Foster checks out the languages and libraries being used to design and verify FPGAs and how they've changed over the last several years. Synopsys' Jonathan Knudsen contends that IT... » read more

2020: A Turning Point In The Chip Industry


At the start of 2020, most of the industry was upbeat and sales forecasts for the year were good. Then the pandemic hit, and fear gripped most of the industry — but not for long. New markets emerged, demand increased, and the levels of innovation went far beyond what had been forecast. While hope is on the horizon that the virus will be contained during 2021, life will not return to the ol... » read more

Week In Review: Design, Low Power


Tortuga Logic was awarded a $12 million SBIR Phase III contract from the US Government to foster the development of advanced hardware security solutions. Ansys will collaborate with Tortuga Logic to advance side-channel leakage analysis workflows. “The award will allow us to rapidly expand our solution to address new classes of hardware weaknesses in the physical domain that are critical to t... » read more

Blog Review: Dec. 23


Cadence's Paul McLellan checks out how Arm is becoming a powerhouse in the server and high-end space with the addition of new R&D and a focus on getting the most out of its architecture. Siemens EDA's Harry Foster continues his look at verification trends in FPGAs by checking out adoption of different simulation and formal technologies. Synopsys' Taylor Armerding looks ahead to 2021 w... » read more

The Crazy Evolution Of Earbuds


Good ideas have a way of continually evolving. Hindsight is wonderful. We can look back over past inventions and proclaim the ones that were successful to be obvious, and those that weren’t as being stupid or flawed. Many successful inventions started off being flawed, but through demand and perseverance, those flaws were eliminated. At the time, I am sure most people thought Da Vinci was ... » read more

RISC-V Verification Challenges Spread


The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies. The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor... » read more

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