category: System-Level Design

category: Auto, Security & Edge AI

Assuring the Integrity of RISC-V Cores and SoCs
By OneSpin Solutions - 21 Aug, 2019 - Comments: 0

The open RISC-V processor architecture is shaking up the intellectual property (IP) and system-on-chip (SoC) worlds. There is great interest and much industry activity underway. However, successful RISC-V core providers will have to verify all aspects of integrity for their designs: functional correctness, safety, security, and trust. SOC developers evaluating potential RISC-V need to check tha... » read more

Facilitating High Level Synthesis from MATLAB generated C C++
By Silexica - 21 Aug, 2019 - Comments: 0

MATLAB is the go-to toolbox for high level algorithm design in many application domains, ranging from signal processing to control systems and data analysis. MATLAB Coder generates executable C/C++ code from MATLAB implementations. However, the performance requirements of these applications often mandate a hardware implementation. SLX FPGA helps transform the auto-generated C/C++ code into a sy... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Aug, 2019 - Comments: 0

Everspin and Seagate inked a patent cross-licensing agreement, including the assignment and licensing of MRAM patents from Seagate to Everspin as well as licensing of specific Tunneling Magnetoresistance (TMR) patents from Everspin to Seagate, which will be used in HDD read/write head technology. Subaru utilized ANSYS' SCADE suite for critical control systems to design and validate embedded ... » read more

Blog Review: Aug. 14
By Jesse Allen - 14 Aug, 2019 - Comments: 0

Cadence's Paul McLellan digs into Mary Meeker's analysis of Internet trends, from growth of the Inernet as a whole to cyber attacks, online finance, and the gig economy. Synopsys' Taylor Armerding warns that the financial services industry is aware of cybersecurity threats, but isn't doing enough to protect its networks and data. Mentor's Colin Walls considers a few cases where writing in... » read more

Debug Tools Are Improving
By Brian Bailey - 12 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. Part one can be found here. Part two... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Aug, 2019 - Comments: 0

Synopsys will acquire QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Based in Germany, QTronic was founded in 2006 and makes a virtual ECU platform as well as a test automation solution with test case generator. Terms of the deal were not disclosed. VeriSilicon uncorked VIP9000, a highly scalable and programmable processor fo... » read more

Are Digital Twins Something For EDA To Pursue?
By Ann Mutschler - 07 Aug, 2019 - Comments: 0

‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing th... » read more

Blog Review: Aug. 7
By Jesse Allen - 07 Aug, 2019 - Comments: 0

Synopsys' Taylor Armerding considers whether ransomware attacks on cities aren't only about money but if there are political motivations for intentionally sowing chaos and dysfunction. Cadence's Paul McLellan takes a look at the different way radio spectrum for 5G is being allocated in the U.S., which recently auctioned 24GHz bands for mmWave, and the rest of the world, which has focused on ... » read more

A Holistic View Of RISC-V Verification
By Nicolae Tusinschi - 07 Aug, 2019 - Comments: 0

Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles published, conference talks presented, and upcoming talks accepted. We tend to focus on the challenges of verifying RISC-V IP cores and sys... » read more

Week In Review: Design, Low Power
By Jesse Allen - 02 Aug, 2019 - Comments: 0

Rambus will acquire Northwest Logic, a maker of digital controller IP for memory, PCIe and MIPI. "Northwest Logic’s category-leading digital controllers fit perfectly with Rambus’ leadership portfolio of high-speed PHY solutions," said Northwest Logic president and CEO Brian Daellenbach. "This deal creates a one-stop-shop for SoC designers working on state-of-the-art applications across a b... » read more

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