category: System-Level Design

category: Auto, Security & Edge AI

Extending RISC-V ISA With Custom Instruction Set Extension
By Codasip - 29 May, 2019 - Comments: 0

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the application needs, without having to pay for area or power that will not be used. One of the groups is special; it has no predefined instruct... » read more

Blog Review: May 29
By Jesse Allen - 29 May, 2019 - Comments: 0

Cadence's Meera Collier traces the evolution of computing through the series of bottlenecks the industry has needed to overcome and what's being done to address the latest one. Mentor's Rebecca Lord checks out the use of differential signals to mitigate the effects of electromagnetic interference, noise, and crosstalk in PCBs. Synopsys' Taylor Armerding considers whether Ireland's slow en... » read more

Pushing Performance: Analysis and Optimization of Multicore Communication with SLX
By Silexica - 29 May, 2019 - Comments: 0

In theory, multicore programming should be simple: Tasks are placed on available cores and allocated a data buffer in the shared memory to communicate data between two tasks. However, the amount of communication resources in the latest multicore SoC is very limited. One cannot deal with all the data communications required by all the tasks without being able to understand communication conte... » read more

System Bits: May 28
By Jeff Dorsch - 28 May, 2019 - Comments: 0

Home robotics get cozier Cornell University’s Guy Hoffman was perplexed when he first saw social robots in stores. “I noticed a lot of them had a very similar kind of feature – white and plasticky, designed like consumer electronic devices,” said Hoffman, assistant professor and the Mills Family Faculty Fellow in the Sibley School of Mechanical and Aerospace Engineering. “Especial... » read more

The Changing Landscape of Hardware-Based Verification And Software Development
By Frank Schirrmeister - 24 May, 2019 - Comments: 0

As the EDA is gearing up for its biggest industry event, the Design Automation Conference (DAC), this year in Las Vegas, it is interesting to observe what is going on in hardware-based development of emulation and prototyping. The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have only grown stronger and are causing changes in the development landsc... » read more

Week In Review: Design, Low Power
By Jesse Allen - 24 May, 2019 - Comments: 0

M&A Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera's revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between Globa... » read more

Blog Review: May 22
By Jesse Allen - 22 May, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that critical infrastructure is still vulnerable to cyber threats, with Kaspersky finding that 42.7% of the industrial control system computers it protected last year were attacked by malware, email phishing, or other threats. Cadence's Paul McLellan listens in as Jon Masters of Red Hat considers how to tackle speculative execution and branch prediction vulne... » read more

Evolution Of Verification Engineers
By Brian Bailey - 22 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

System Bits: May 21
By Jeff Dorsch - 21 May, 2019 - Comments: 0

Washable, wearable energy devices for clothing Researchers at the University of Cambridge collaborated with colleagues at China’s Jiangnan University to develop wearable electronic components that could be woven into fabrics for clothing, suitable for energy conversion, flexible circuits, health-care monitoring, and other applications. Graphene and other materials can be directly incorpor... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 May, 2019 - Comments: 0

Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

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