category: System-Level Design

category: Auto, Security & Edge AI

Of Aero Shows And Safety
By Janusz Kitel - 28 Mar, 2019 - Comments: 0

At the end of February, I attended the Aero Show in India - and what a show it was. So many exhibitors from around the world, including all main players from the commercial and military sides of the aerospace industry. Visitors could see everything required to build a modern aircraft: from small components like specialized ICs, cables and connectors up to big parts, such as the jet engines... » read more

Digital Twins Deciphered
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

High-Speed Communications: On The Road Again
By Mike Gianfagna - 28 Mar, 2019 - Comments: 0

Lately, we’ve had quite a lot of trade show participation. I discussed ISSCC last month. I will be careful right now to state that ISSCC is a technical conference and not a trade show. The organizers are quite particular about that. Nonetheless, we were invited to demonstrate our high-speed SerDes there, and we got a lot of great questions from a lot of very smart people. Since ISSCC, we�... » read more

Utilizing More Data To Improve Chip Design
By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

RISC-V At Embedded World
By Jo Windel - 28 Mar, 2019 - Comments: 0

As we arrive back from a busy, and unusually warm, Embedded World 2019 and recall the many interesting discussions we had over the three-day show, one thing is most certainly clear: This is the Mobile World Congress (MWC) event for Nuremberg. Its many halls were jam-packed with technology from a wide variety of sectors but also with an array of application focal points. There was everything ... » read more

The Automation Of AI
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Delivering Superior Throughput For EDA Verification Workloads
By Cadence - 27 Mar, 2019 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

Billion-Gate Design Connectivity
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

Formal Apps Take The Bias Out Off Functional Verification
By Mentor, a Siemens Business - 27 Mar, 2019 - Comments: 0

The Questa Formal Apps automate common formal analysis tasks, providing a multiple set of tools for formal verification experts and novices alike. Each of these automated tasks are integrated into a holistic, formal analysis workflow that allows you to use what you need when you need it. This paper describes common verification challenges and how specific Questa Formal Apps handle them along wi... » read more

Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained Parallelism
By Synopsys - 27 Mar, 2019 - Comments: 0

Non-stop growth in design size and complexity makes it more difficult than ever for verification teams to keep up with project demands and product goals. According to the Synopsys 2017 Global User Survey, “Verification taking longer than planned” is the top reason for tapeout delays, and “Simulation runtime performance” is the top challenge for verification. Since regression test turn-a... » read more

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