category: System-Level Design

category: Auto, Security & Edge AI

Debug Changes At Advanced Nodes
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a commensurate amount of software complexity. The key is how to maintain or reduce time to market, and that requires a different way of approaching the problem. » read more

Multicore Software Design For An LTE Base Station
By Silexica - 27 Mar, 2019 - Comments: 0

This paper presents a typical base station design scenario, where decisions about HW/SW partitioning, the number of processing elements, and operational system parameters, among other things, need to be made early on by system architects. SLX determines the impact of these various design decisions and parameter selections, while exploring different target architecture configurations and checks ... » read more

Blog Review: Mar. 27
By Jesse Allen - 27 Mar, 2019 - Comments: 0

Rambus' Steven Woo takes a look at the memory requirements of neural networks and why some companies are using on-chip memory while others are using HBM2 or GDDR6. Cadence's Lana Chan  observes growing momentum for NVMe and highlights some new features in the latest specification that are pushing mainstream adoption forward. Mentor's Matthew Ballance contends that when it comes to adopti... » read more

When Correct Is Not Enough: Formal Verification of Fault-Tolerant Hardware
By OneSpin Solutions - 27 Mar, 2019 - Comments: 0

Once upon a time, hardware functional verification was all about ensuring that a circuit would perform its specified functions under all legal input stimuli. Today, though, gaining confidence that a hardware design is correct is often not enough. Several industries, including automotive, medical, and aerospace, rely on safety-critical hardware to keep people safe. Other systems, for example, in... » read more

Data-Driven Verification Begins
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss data-driven verification with Yoshi Watanabe, senior software architect at Cadence; Hanan Moller, systems architect at UltraSoC; Mark Conklin, principal verification engineer at Arm; and Hao Chen, senior design engineer at Intel. What follows are excerpts of that conversation, which was conducted in front of a live audience at DVCon. (L-R) Yosh... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Mar, 2019 - Comments: 0

Synopsys announced several new products: a new test family, a physical verification solution, and a software library for neural net SoCs. TestMAX, the new family of test products, includes soft error analysis and X-tolerant logic BIST for automotive test and functional safety requirements. TestMAX enables test through functional high-speed interfaces and supports early validation of DFT logi... » read more

Blog Review: Mar. 20
By Jesse Allen - 20 Mar, 2019 - Comments: 0

Cadence's Paul McLellan argues that rapid improvements in the performance of general-purpose computing led to a lack of innovation in domain-specific architectures, but as scaling slows, they're entering a new golden age. In a video, Mentor's Colin Walls takes a look at the use of floating point in an embedded application and some of the pitfalls associated with it. Synopsys' Taylor Armer... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Mar, 2019 - Comments: 0

M&A Nvidia will acquire Mellanox for $6.9 billion in cash, the largest deal in the chipmaker's history. Traditionally a PC GPU company, Nvidia has made a push into high-performance computing, particularly for AI workloads. Founded in 1999, Israel-based Mellanox focuses on end-to-end Ethernet and InfiniBand interconnect solutions and services for servers and storage. According to Nvidia, Me... » read more

Blog Review: Mar. 13
By Jesse Allen - 13 Mar, 2019 - Comments: 0

Mentor's Tom Fitzpatrick questions whether deep learning approaches can really help improve coverage in modern, complex designs. Cadence's Paul McLellan listens in at MWC as Huawei chairman Guo Ping defends the company's security practices and shows where its heading in 5G. Synopsys' Eric Huang checks out the newly announced USB4 specification, changes to previous USB names, and a few things ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Mar, 2019 - Comments: 0

Cadence debuted Denali Gen2 IP for LPDDR5/4/4X in TSMC's 7nm FinFET process technology. The offering consists of PHY, controller and Verification IP. It supports both the pre-release LPDDR5 standard and LPDDR4/4X devices as well as Arm AMBA AXI buses and reliability features like in-line error correcting codes. The LPDDR5 standard provides up to 1.5x bandwidth over LPDDR4 and LPDDR4X. The US... » read more

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