category: System-Level Design

category: Auto, Security & Edge AI

Prototyping Building Blocks
By Tom De Schutter - 28 Sep, 2017 - Comments: 0

Lego has existed for 85 years. The company was founded August 10, 1932, and after all these years, the concept of building structures big and small still hasn’t lost any of its charm. For my children, now 10 and 12, it is probably the most played with toy throughout their childhood. As with any new purchase, they initially and carefully build the specific design for the instructions included ... » read more

System Coverage Undefined
By Brian Bailey - 28 Sep, 2017 - Comments: 1

When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over. Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more

Finite State Machine Synthesis In Programmable Circuits
By Radek Nawrot - 28 Sep, 2017 - Comments: 0

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions? For me, one of my summer break ponderings was thinking back on a trick I learned while working with my colleagues at the Silesian University of Technology. C... » read more

Making Software Development Equivalent For Models And Boards
By Jason Andrews - 28 Sep, 2017 - Comments: 0

Selected Cortex-M processors include the instruction trace microcell (ITM) to help understand system behavior. Although it can provide other types of trace, the ITM is commonly associated with printf() output and event tracing from applications and operating systems. Historically, Fast Model systems have used semihosting or UART models to provide character and file I/O when running software on ... » read more

Verifying AI, Machine Learning
By Ed Sperling - 28 Sep, 2017 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down to talk about artificial intelligence, machine learning, and neuromorphic chips. What follows are excerpts of that conversation. SE: What's changing in [getkc id="305" kc_name="machine learning"]? Brinkmann: There’s a real push toward computing at the edge. ... » read more

Talking The Talk On Training
By Mike Gianfagna - 28 Sep, 2017 - Comments: 1

In my prior post, I discussed the value of good design flow training. A properly executed program can turn average engineers into above average problem solvers with the right tools and techniques. We got to thinking about this opportunity quite seriously at eSilicon. Is there a way to develop a focused, intense training program to create a new “army” of elite designers? In short, we thin... » read more

Tech Talk: TCAM
By Ed Sperling - 28 Sep, 2017 - Comments: 0

Dennis Dudeck, IP solutions FAE at eSilicon, talks about how to save power and area with ternary content addressable memory. https://youtu.be/y1FhdoNdzOw » read more

Verification’s Breaking Points
By Ann Mutschler - 28 Sep, 2017 - Comments: 2

Verification efficiency and speed can vary significantly from one design to the next, and that variability is rising alongside growing design complexity. The result is a new level of unpredictability about how much it will cost to complete the verification process, whether it will meet narrow market windows, and whether quality will be traded off to get a chip out on time in the hopes that it c... » read more

DVCon Europe Takes Over Munich October 16-17
By McKenzie Ross - 28 Sep, 2017 - Comments: 0

DVCon Europe is on the horizon, and this year's program should prove to be very timely. Chips and systems are getting more complex, verification is becoming more difficult, and formal has emerged as a critical piece of the verification suite The lineup this year tackles some key issues facing a changing semiconductor landscape. During a Monday tutorial, “Next Generation ISO 26262-based De... » read more

A Simple Way To Debug IIP-Based Designs And SoCs
By Synopsys - 27 Sep, 2017 - Comments: 0

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. This whitepaper presents the concept of debugging with “real time simulation data” using Verdi Transaction Debug Platform (protocol analyzer, waveform viewer, source code browser) and show its benefits by taking a few generic USB... » read more

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