category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: July 1
By Jesse Allen - 01 Jul, 2015 - Comments: 0

On the eve of his retirement, Cadence's Richard Goering takes a look back at 30 years of covering EDA: the highlights, the lowlights, and the headlights shining into the future. Established nodes are experiencing a much higher demand than one might normally expect at this point in their lifecycle. Mentor's Michael White examines the dynamics and market forces behind the longevity, and the ch... » read more

System Bits: June 30
By Ann Mutschler - 30 Jun, 2015 - Comments: 0

Implantable drug-delivery chip An implantable, microchip-based device developed by MIT spinout Microchips Biotech may soon replace the injections and pills now needed to treat chronic diseases. The company partnered with Teva Pharmaceutical to commercialize its wirelessly controlled, implantable, microchip-based devices that store and release drugs inside the body over many years. [caption id... » read more

The Future Of Moore’s Law
By Ed Sperling - 29 Jun, 2015 - Comments: 1

Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at [getentity id="22819" comment="GlobalFoundries"]; Charlie Cheng, CEO of [getentity id="2... » read more

The Week In Review: Design/IoT
By Jesse Allen - 26 Jun, 2015 - Comments: 0

IP Sonics released the latest version of the company's flagship NoC, which expands on their interleaved multi-channel technology and includes new layout optimization features for design flows based on modern physical synthesis and place & route tools. Synopsys extended its PCI Express 4.0 IP to support RAS features to help designers ensure data integrity and increase data protection i... » read more

Intel Plus Altera
By Ed Sperling - 25 Jun, 2015 - Comments: 0

Since the Intel-Altera deal reached the handshake phase earlier this month, there have been a lot of theories being forwarded and a lot of questions being raised. And there have been very few answers, in part because the deal isn't finalized yet and in part because this marriage will take time to play out in the market—maybe years. But along with the GlobalFoundries-IBM pairing, this is th... » read more

More Data, Different Approaches
By Ed Sperling - 25 Jun, 2015 - Comments: 0

Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

EDA’s Clouded Future
By Brian Bailey - 25 Jun, 2015 - Comments: 0

There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast. “This has been driven by ... » read more

What Is A System Now?
By Ann Mutschler - 25 Jun, 2015 - Comments: 0

Defining a system used to be relatively straightforward. But as systems move onto chips, and as those chips increasingly are connected with applications and security spanning multiple devices, the definition is changing. This increases the complexity of the design process itself, and it raises questions about how chips and software will be designed and defined in the age of the [getkc id="76... » read more

Wrong Verification Revolution Offered
By Brian Bailey - 25 Jun, 2015 - Comments: 0

SoC design traditionally has been an ad-hoc process, with implementation occurring at the register transfer level. This is where verification starts, and after the blocks have been verified, it becomes an iterative process of integration and verification that continues until the complete system has been assembled. But today, this methodology has at least two major problems, which were addres... » read more

Tear Down The Wall Between Front-End And Back-End Teams
By Kurt Shuler - 25 Jun, 2015 - Comments: 1

As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy