category: System-Level Design

category: Auto, Security & Edge AI

System Bits: March 3
By Ann Mutschler - 03 Mar, 2015 - Comments: 0

Observing antiferromagnetic order in ultracold atoms Rice University researchers have simulated superconducting materials and made headway on a problem that’s vexed physicists for nearly three decades using ultracold atoms as a stand-in for electrons. The research team, led by Rice, included researchers from Ohio State University, Universidade Federal do Rio de Janeiro, University of Cal... » read more

The Week In Review: Design/IoT
By Jesse Allen - 27 Feb, 2015 - Comments: 0

Mergers & Acquisitions NXP acquired Quintic’s Bluetooth Low Energy and Wearable businesses, adding BLTE to their low power RF-connectivity portfolio. The team of approximately 65 is expected to join NXP when the deal closes in Q1 2015. Tools Cadence unveiled the integration of Forte's Cynthesizer with their own C-to-Silicon Compiler. The result is the Stratus high-level synthesis... » read more

Mentor Graphics Buys Tanner EDA
By Ed Sperling - 26 Feb, 2015 - Comments: 4

By Ed Sperling & Brian Bailey [getentity id="22017" e_name="Mentor Graphics"] has just purchased [getentity id="22561" e_name="Tanner EDA"] for an undisclosed sum, according to sources close to the deal. The acquisition moves Mentor squarely into the analog and mixed signal tools world, while positioning it to play a much bigger role in the Internet of Things market. Mentor isn't t... » read more

Obsolescence Isn’t Always Good
By Ed Sperling - 26 Feb, 2015 - Comments: 2

One of the main reasons smartphones are pervasive around the globe is that their cost is subsidized. They can be replaced every couple of years with minimal pain as designs get slicker, more energy-efficient, and new features are added such as better screens or better performance. That works particularly well when a consumer's out-of-pocket expenses after trading in an older model are basically... » read more

Partition Lines Growing Fuzzy
By Ed Sperling - 26 Feb, 2015 - Comments: 0

For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

Incremental Design Methodologies
By Brian Bailey - 26 Feb, 2015 - Comments: 0

There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more

IP Market Booms At Advanced Nodes
By Ann Mutschler - 26 Feb, 2015 - Comments: 0

As [getkc id="81" kc_name="SoC"] design and manufacturing costs rise, system OEMs are wringing as much of that increase as they can from ASIC vendors. The result is that engineering teams on the design and test side are being constrained by budgets at a time when complexity is rising and time-to-market pressures are increasing. At least one segment is benefiting from directly this. Budgetary... » read more

Custom Versus Platform Design
By Ed Sperling - 26 Feb, 2015 - Comments: 0

The increase in [getkc id="81" kc_name="SoC"] complexity is being mirrored by a rise in complexity within the markets that drive demand for those chips. The upshot is that a push toward greater connectivity, lower power and better performance—and all for a minimal cost—has turned the pros and cons for custom design vs. platforms and superchips into a murky decision-making process. For t... » read more

First Time Success And Cost Control
By Brian Bailey - 26 Feb, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Inside The Hybrid Memory Cube
By Dhananjay Wagh - 26 Feb, 2015 - Comments: 0

The memory bandwidth requirements for today’s high-performance computing applications and next-generation networking applications have increased beyond what conventional memory architectures can provide. For example in a typical 400G networking application, packet buffer bandwidth requirement could be as high as 2,000 Gb/s. Achieving this level of bandwidth using the latest DDR4 memory te... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy