System Bits: March 24


A better band-aid UC Berkeley engineers are working on a bandage that can detect bedsores before they are visible - while recovery from them is still possible. Leveraging flexible electronics advancements, the researchers collaborated with colleagues at UC San Francisco to create their “smart bandage” that uses electrical currents to detect early tissue damage from pressure ulcers as th... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions Silvaco acquired Invarian, anticipating integration of Invarian's methodology will accelerate adoption of concurrent power-voltage-thermal analysis. Legal A U.S. District Court judge ordered Kilopass to pay $5.5 million to Sidense for legal fees incurred in Kilopass' patent infringement suit against Sidense. That lawsuit was  dismissed in 2012. Sidense filed... » read more

Blog Review: March 18


How do you quantify effort spent in FPGA verification? Mentor's Harry Foster tackles the question in his latest installment of the Wilson Research Group functional verification study. A new frontier of design challenges is rapidly emerging, according to ARM CEO Simon Segars. Cadence's Brian Fuller brings us his keynote address at CDNLive. Synopsys' Tushar Mattu is back with more on AXI VI... » read more

System Bits: March 17


Symmetry in graphene growth According to Rice University researchers, what lies beneath growing islands of graphene is important to its properties. The team analyzed patterns of graphene – a single-atom-thick sheet of carbon – grown in a furnace via chemical vapor deposition and discovered that the geometric relationship between graphene and the substrate, the underlying material on whi... » read more

First Time Success And Cost Control


First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions NXP added to its list of recent acquisitions with Athena SCS, a UK-based provider of embedded software and cryptography for smart cards and NFC. Lattice Semiconductor closed its all-cash $606.6 million acquisition of Silicon Image. Tools Cadence unveiled the Innovus Implementation System. The physical implementation tool sports massively parallel architect... » read more

Blog Review: March 11


How are sensors like a scallop's eyes? Rambus' Patrick Gill guides you through day in the life of the mollusk to show how inspiration for IoT was found in the sea. Cadence's Dimitry Pavlovsky discusses some of the intricacies associated with creating VIP for processor interconnect systems such as CHI, and how other tools are necessary to complete the task. Following Google's warning of a ... » read more

System Bits: March 10


Surviving entanglement breakdown Researchers at MIT have discovered that preserving the fragile quantum property known as entanglement isn’t necessary to reap benefits. By way of background, the MIT team reminded that the promise of quantum information processing, i.e., solving problems that classical computers can’t, as well as perfectly secure communication depends on a phenomenon cal... » read more

The Week In Review: Design/IoT


Mergers & Acqusitions Mentor Graphics acquired Tanner EDA, bolstering their position in tools for analog, mixed-signal and MEMs. Terms of the deal were not disclosed. NXP joins forces with Freescale. The merger carries a $16.7 billion price tag and potentially creates a new leader in the automotive and MCU markets. Standards Accellera sent UVM 1.2 off to the IEEE P1800.2 working... » read more

Blog Review: March 4


Is gate-level simulation still necessary? Mentor's Gordon Allan asserts it is, and gives a list of reasons why the pain is worth the peace of mind. Synopsys' Aron Pratt concludes his series on parameterization strategies with a process that allows the testbench to make use of parameterized interfaces without imposing limits on VIP access. Should you use EUV or quadruple patterning for 7nm... » read more

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