category: System-Level Design

category: Auto, Security & Edge AI

The End Of Automated Patent Trolls?
By Brian Bailey - 27 Feb, 2014 - Comments: 2

I have written several articles and blogs recently about the [getkc id="16" comment="patent"] system, and readers of What Were They Thinking know that I like to poke fun at patents that never should have been issued because they are obvious, silly or would never actually be able to work. There are patents that cover using a laser pointer to play with a cat, to water a Christmas tree or to creat... » read more

EDA Hungers For Growth
By Brian Bailey - 27 Feb, 2014 - Comments: 1

Look at the top line numbers provided by the EDA industry consortium (EDAC) and it appears as if the industry is doing well. In 2010, revenue was $5.285 billion. That number increased to $6.218 billion in 2011, and again to $6.529 billion in 2012, a 9.5% annual growth rate that would satisfy most investors. But the numbers do not tell the whole story. There is an interesting divide growing betw... » read more

Design And Verification Survey Results
By Graham Bell - 27 Feb, 2014 - Comments: 1

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins. This year, I would like ... » read more

Time to mend the EE / CS divide
By Kurt Shuler - 27 Feb, 2014 - Comments: 0

There’s been a lot of news out the last few weeks about the future of our industry, and although these news flashes may seem unrelated, they are quite correlated. First, there was the disturbing news in Mark LaPedus’ article here on Semiconductor Engineering, “EUV Suffers New Setback,” portending a rough ride for the commercialization of EUV lithography. EUV will be needed to create ... » read more

Is Verification At A Crossroads?
By Ann Mutschler - 27 Feb, 2014 - Comments: 1

As SoC verification methodologies and technologies have continued to mature, it’s an interesting time for engineering teams as they look to meet time to market goals and cut costs in an environment of cutthroat profit margins. Whether it is hardware emulation, FPGA prototyping, virtual prototyping or traditional software simulation, each platform has its strengths and drawbacks, with overl... » read more

Virtual Prototypes For Early Software Development
By Various Writers - 26 Feb, 2014 - Comments: 0

In previous white papers, we've looked at the demands of the rapidly changing market and how the use of virtual prototypes has evolved to help meet them. In this white paper, we look specifically at the challenges of developing some of the hardware-dependent software layers - namely boot ROM code, OS bring-up, driver development - used in fast-evolving mobile devices and how to use virtual prot... » read more

Plug-And-Play Test Strategy For 3D ICs
By Various Writers - 26 Feb, 2014 - Comments: 0

As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die. Solutions for 3D IC test are developing rapidly and are based on mature technologies. In this paper, we describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die... » read more

Blog Review: Feb. 26
By Ed Sperling - 26 Feb, 2014 - Comments: 0

Got enough time for verification? How about a verification conference? In preparation for DVCon, Real Intent’s Graham Bell grills a panel of experts on where design ends and verification begins. The answer: It depends. Mentor’s Dennis Brophy points to the new version of the Universal Verification Methodology as a reason to attend DVCon next week. Even if you don’t plan to attend, ther... » read more

Maximizing Verification Effectiveness Using Metric-Driven Verification
By Various Writers - 26 Feb, 2014 - Comments: 0

This paper introduces the Cadence Incisive Verification Kit as a golden example of how to maximize verification effectiveness by applying metric-driven verification (MDV) in conjunction with the Universal Verification Methodology (UVM). MDV provides an overarching approach to the verification problem by transforming an open-ended, open-loop verification process into a manageable, repeatable, de... » read more

System Bits: Feb. 25
By Ann Mutschler - 25 Feb, 2014 - Comments: 0

A faster Internet While light is capable of carrying vast amounts of information, to utilize its potential, the laser light needs to be as spectrally pure—as close to a single frequency as possible. The purer the tone, the more information it can carry. For decades researchers have been trying to develop a laser that comes as close as possible to emitting just one frequency. Today's world... » read more

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