category: System-Level Design

category: Auto, Security & Edge AI

System Bits: August 20
By Ann Mutschler - 20 Aug, 2013 - Comments: 0

RF jammer technology To thwart electronic warfare technology, a research team at the Georgia Tech Research Institute (GTRI) is developing a new generation of advanced radio frequency (RF) jammer technology as part of a project known as Angry Kitten by using commercial electronics, custom hardware development, novel machine-learning software and a unique test bed to evaluate unprecedented level... » read more

The Week In Review: Aug. 16
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Manufacturing Equipment giant Applied Materials added three extra letters company president Gary Dickerson’s title—CEO. Mike Splinter, who has served as the company’s CEO since 2003, will become executive chairman of the board of directors. Dickerson was the CEO of Varian, which Applied Materials acquired in 2011. Synopsys introduced a Dolby decoder for its ARC process... » read more

Blog Review: Aug. 14
By Ed Sperling - 14 Aug, 2013 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang unveils the fastest USB ever. The seat belt is extra. Mentor’s Nazita Saye sees the light—well, at least a refracted version of it—through the lens of a plastic bottle. This one is a real energy saver for the money, even if you have to forfeit the recycling fee. Check out the link. Cadence’s Brian Fuller takes a sledgehammer to the semicond... » read more

System Bits: August 13
By Ann Mutschler - 13 Aug, 2013 - Comments: 0

Analyzing ad hoc networks Now that the basic protocols of the Internet are more than 30 years old, network scientists are increasingly turning attention to ad hoc networks in which communications networks set up, on the fly, by wireless devices. Here, unsolved problems still abound. Most theoretical analyses of ad hoc networks have assumed that the communications links within the network ar... » read more

Experts At The Table: Automotive Electronics
By Ann Mutschler - 09 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss the opportunities in automotive electronics with Alexandre Palus, principal SoC architect at Altera; Aveek Sarkar, VP of product engineering & support at Apache; Mladen Nizic, engineering director, mixed signal solution at Cadence; and Stephen Pateras, product marketing director, silicon test solutions at Mentor Graphics. W... » read more

Experts At The Table: Automotive Electronics
By Ann Mutschler - 02 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss the opportunities in automotive electronics with Alexandre Palus, principal SoC architect at Altera; Aveek Sarkar, VP of product engineering & support at Apache; Mladen Nizic, engineering director, mixed signal solution at Cadence; and Stephen Pateras, product marketing director, silicon test solutions at Mentor Graphics. W... » read more

Blog Review: July 31
By Ed Sperling - 31 Jul, 2013 - Comments: 0

By Ed Sperling Wherever you turn in IC design, there’s always someone talking about future problems involving the interconnect. Cadence’s Brian Fuller puts the latest speech by North Carolina State professor Paul Franzon in historical perspective—or at least in the shadow of the last dire prediction by Intel’s Mark Bohr two decades ago. Incidentally, Bohr’s warning turned out to be r... » read more

System Bits: July 30
By Ann Mutschler - 30 Jul, 2013 - Comments: 0

Controlling nanomaterials To find out why some sets of flat nanocrystals arrange themselves in an alternating, herringbone style even though it wasn’t the simplest pattern, University of Pennsylvania researchers turned to experts in computer simulation at the University of Michigan and the Massachusetts Institute of Technology. The result of the collaboration gives nanotechnology research... » read more

Garbage Or Treasure?
By Jon McDonald - 27 Jul, 2013 - Comments: 0

By Jon McDonald “Garbage in, garbage out” is a very appropriate axiom to keep in mind as you consider what kind of system-level modeling to invest in. Unfortunately this can be complicated by considering another piece of wisdom that often applies as well: “One mans trash is another’s treasure.” What might be an inappropriate abstraction for one type of analysis may be very accepta... » read more

FPGA Verification with Assertions: Why Bother?
By Various Writers - 27 Jul, 2013 - Comments: 0

This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions. To download this white paper, click here. » read more

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