category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: July 24
By Ed Sperling - 24 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster unleashes part six of the Wilson Research Group functional verification study, this segment digging deeper into the time spent in verification. The numbers have surpassed time spent on the design side, which either means the front-end tools are getting better or the verification problem is becoming more difficult. Cadence’s Brian Fuller interviews I... » read more

System Bits: July 23
By Ann Mutschler - 23 Jul, 2013 - Comments: 0

Bottom-up nanoribbons Concentric hexagons of graphene grown in a furnace at Rice University represent the first time anyone has synthesized graphene nanoribbons on metal from the bottom up — atom by atom. As seen under a microscope, the layers brought onions to mind, according to Rice chemist James Tour, until a colleague suggested flat graphene could never be like an onion. “So I said,... » read more

Why Should A Decision Be Delayed?
By Jon McDonald - 22 Jul, 2013 - Comments: 0

By Jon McDonald Way back in college when I first learned about “delayed binding” I was absolutely ecstatic. In its most general interpretation this is not just a software concept. It’s a way of life. The important part of the concept is to understand that a decision or an action should not be taken until it needs to be taken. This is a relatively simple concept with very broad implica... » read more

The Week In Review: July 19
By Ed Sperling - 19 Jul, 2013 - Comments: 0

By Ed Sperling Synopsys rolled out a 28nm data converter IP portfolio for analog-to-digital and digital-to-analog converters, as well as integrated PLLs. Synopsys says the new architecture saves up to 76% of the power and 86% of area. Mentor Graphics added intelligent software-driven verification to its functional verification platform. New is the ability to automatically generate embedded ... » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 19 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: When it comes... » read more

Executive Briefing: Prakash Narain
By Ed Sperling - 12 Jul, 2013 - Comments: 0

Real Intent CEO Prakash Narain talks with System-Level Design about where are the pain points in verification; different types of signoff; the impact of third-party IP, and can the tools industry keep up with the rising complexity in semiconductor design. [youtube vid=C25VMRDXGAQ] » read more

The Week In Review: July 12
By Ed Sperling - 12 Jul, 2013 - Comments: 0

By Ed Sperling Cadence rolled a new version of its layout suite of tools for electrically aware designs, allowing design teams to check on electrical issues while the layout is being done. The company says this can reduce circuit design time by up to 30%, in addition to optimizing for performance and area. Cadence also announced a deal with Global Unichip, which successfully taped out a 20nm ... » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 12 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: Is it possib... » read more

Blog Review: July 10
By Ed Sperling - 10 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster rolls out part four of his epic functional verification study, this one on design and verification reuse. If you work in the verification world, pounce. Cadence’s Brian Fuller looks back over a quarter century of technology—and what the average salary of a hardware design engineer will be in a 15 years: $499,000. But what will a cup of coffee cost?... » read more

System Bits: July 9
By Ann Mutschler - 09 Jul, 2013 - Comments: 0

New quantum computing algorithm Researchers at the University of California, San Diego, have proposed a new algorithm for quantum computing that they believe will speed a particular type of problem…but swifter calculations would come at the cost of greater physical resources devoted to precise timekeeping. The algorithm would be used to conduct a task called an unstructured search. The go... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy