category: System-Level Design

category: Auto, Security & Edge AI

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By Jon McDonald - 29 Nov, 2012 - Comments: 0

By Jon McDonald Many people—engineers especially, myself included—are naturally biased against change. To get an organization to change takes significant energy. This isn’t a new trend. Much of the sentiment of the camp against change can be summed up by referring back to an 1899 quote from Missouri Sen. Willard Vandiver: “… frothy eloquence neither convinces nor satisfies me. I am f... » read more

Parallel Universes
By Ed Sperling - 29 Nov, 2012 - Comments: 0

There are no rules for knowing when to step out of the box. Good timing is everything, and that may have been one of the greatest talents of the late Steve Jobs. Knowing when, in Apple’s terminology, to “Think Different,” is every bit as important as the act of thinking differently—particularly when you realize that most of Apple’s big wins since the iPod stormed onto the consumer ele... » read more

Taming The Challenges Of 20nm Custom/Analog Design
By Various Writers - 29 Nov, 2012 - Comments: 0

Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The solution lies not just in improving individual tools, but in a new design methodology that allows rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers. To view this white paper, click here. » read more

Questa Covercheck: An Automated Code Coverage Closure Solution
By Various Writers - 29 Nov, 2012 - Comments: 0

This white paper explores the debugging aspect of code coverage closure, and how Questa CoverCheck’s unique ability of formal technology can automatically generate simulation exclusion files to improve code coverage results while reducing the amount of time wasted trying to hit unreachable states. To download this white paper, click here. » read more

The Agony Of Choice
By Frank Schirrmeister - 28 Nov, 2012 - Comments: 0

By Frank Schirrmeister In my last post on “The Complexity of System Development and Verification” I outlined five main use models for verification at four levels of scope, enabled by seven execution engines. So how exactly do users choose between the different execution engines to run hardware and software together before the actual chip is available? It is far from trivial. The seven engi... » read more

The Growing Verification Challenge
By Ed Sperling - 28 Nov, 2012 - Comments: 0

System-Level Design talks with Charles Janac of Arteris, Frank Schirrmeister of Cadence, Venkat Iyer of Uniquify and Adnan Hamid of Breker Verification Systems about the growing difficulty of verifying complex SoCs and what lies ahead. [youtube vid=zUB4_t9teE8] » read more

The Essential Tool Kit
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Is there an essential chip design tool kit today that has only the ‘must haves?’ Sure, this sounds like a straightforward question, but the answer really depends on what process node the design will be manufacturing on. According to Jon McDonald, technical marketing engineer for the design and creation business at Mentor Graphics, there’s actually nothi... » read more

The New Mixed-Signal Flow
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler We are on the cusp of the mixed-signal era. Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, no longer are sufficient. They lead to excess iteration and prolonged design cycle time. Today’s mixed-signal designs require a new approach that enables design teams to be as efficient as possible productivity... » read more

The Growing Confidence Gap In Verification
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling It’s no surprise that verification is getting more difficult at each new process node. What’s less obvious is just how deep into organizations the job of verifying SoCs and ASICs now extends. Functional verification used to be a well-defined job at the back end of the design flow. It has evolved into a multi-dimensional, multi-group challenge, beginning at the earliest st... » read more

Calculating Emulation’s Complex Cost Of Ownership
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Hardware emulation or hardware-assisted verification –whichever term you choose—has been around for decades. But until recently it has seen only modest adoption due to the high cost, long set-up time, power and IT requirements, among other things. But with simulation running out of steam between 50 and 100 million gates, this specialized hardware makes a ... » read more

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