The Complexity Of System Development And Verification


By Frank Schirrmeister The electronics industry is undergoing a fast transition towards new paradigms for system development and verification as traditional development methods reach their breaking points. Developing a system development and verification environment can become a costly undertaking, and can involve many direct and sometimes even more hidden cost. To understand the cost aspects,... » read more

Executive Briefing: Aart de Geus


By Ann Steffora Mutschler EDA, IP, semiconductors, electronics…actually every industry is woven into the tapestry of a global macroeconomic system. Running a business successfully within this environment requires a unique skillset; at once entrepreneurial as well as wise and discerning. System-Level Design sat down with Aart de Geus, chairman and co-CEO of Synopsys, to discuss these iss... » read more

Thanks For The Memories


By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

Virtual Prototyping Is Golden


By Nithya Ruff Watching the Olympics this past summer was quite exciting. I enjoyed seeing athletes at the peak of their performance and multiple records broken in many sports. What we don’t see is the years of practice and work behind this excellence. These athletes work at the technique, strength, endurance and mental attitude of winning. To me, this is no different than the work that goes... » read more

SMP, Asymmetric Multi- processing And The HSA Foundation


When we hear the term “multiprocessing,” we often associate it with “symmetric multiprocessing (SMP).” This is because of SMP’s initial prevalence in the high-performance computing world, and now in x86/x64 servers and PCs. However, it’s been known for years that SMP’s ability to scale performance as the number of cores increases is poor. (For more information on SMP’s inability... » read more

You Get What You Want


By Frank Ferro Now that the iPhone 5 hype is quieting down, the discussion has turned to the A6 chip that is powering this must-have device. There is much speculation on what is inside the A6 processor. Is it a dual-core A15 or a custom architecture? Is it a ‘big.LITTLE’ architecture? What speed are cores running at—1.2GHz? Others argue that the graphics processor is of equal importance ... » read more

Choosing The Right Kite


By Jon McDonald At my 16-year-old son’s suggestion the two of us have been taking kite-surfing lessons. Last weekend part of the lesson covered the different kinds of kites, how they compare and reasons to use one versus another. One of the points made by the instructor was the need to have different kites for different conditions. It’s such a simple concept, but one that was forgotten ... » read more

Economic Resilience


Check out the lines at the Apple store for iPhones and you have to wonder what all the economists are worrying about. It seems incongruous, but the electronics industry is faring well in the face of a global economy that is flat in the best of places, sluggish in others, and faltering everywhere else. So what’s up? Mobile computing is the answer. While predictions of the computer’s de... » read more

Experts At The Table: FPGA Prototyping Issues


By Ed Sperling System-Level Design sat down to discuss challenges in the FPGA prototyping world with Troy Scott, product marketing manager at Synopsys; Tom Feist, senior director of marketing at Xilinx; Shakeel Jeeawoody, vice president of marketing at Blue Pearl Software; and Ralph Zak, business development director at EVE. What follows are excerpts of that discussion. SLD: As we go forwar... » read more

Where Does It Hurt?


By Ed Sperling The IC design industry is feeling a new kind of pain—this one driven by uncertainty over architectural shifts, new ecosystem interactions and new ways to account for costs. As mainstream ICs move from 50/45/40nm to around 32/28/22nm, there are only two choices for design teams—continue shrinking features or stack dies. In many cases, the ultimate solution may be a combina... » read more

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