category: System-Level Design

category: Auto, Security & Edge AI

Best Practices In Verification
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler The advent of advanced verification methodologies such as the UVM and its predecessors VMM and OVM has changed the verification landscape in many ways. Design and verification teams used to worry about simulator performance (i.e., how fast the simulator runs a particular test case), but the introduction of constrained-random stimulus and functional coverage and associ... » read more

Being Different Is Bad
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Today’s SoCs contain as much as 80% existing IP that either has been re-used from previous projects or obtained from a third party. Models are created of this hardware IP, as well as new portions of the design, in order to create a virtual prototype that allows the engineering team to see the complete system by running software and applications. While this a... » read more

ROM Code First
By Achim Nohl - 23 Aug, 2012 - Comments: 0

By Achim Nohl Finally, nine months after the next-generation SoC project was kicked off, the first prototype board has finally arrived! There are just six months left to get Android and Linux up and running. Because Android should take full advantage of the latest hardware additions, let’s make sure we get it ported as quickly as possible. Unfortunately, it’s not that easy. Before you c... » read more

From Hype To Reality
By Kurt Shuler - 23 Aug, 2012 - Comments: 0

By Kurt Shuler My purpose in this article is to explain Gartner Research’s Hype Cycle and relate it to the Technology Adoption Lifecycle popularized by Geoffrey Moore’s book, “Crossing the Chasm.” These two models can be used together to provide a combined picture of market expectations and expected technology adoption rates, but people often get the timeframes and takeaways wrong. So ... » read more

Verify This
By Frank Ferro - 23 Aug, 2012 - Comments: 0

By Frank Ferro Verify this? No, New Jersey in me is not coming out. This is not a pejorative; it is simply a request and a question. It is a request by SoC designers to the verification team. It is also the verification’s team response when they realize the enormity of the task: “You want me to verify this?” As I continue the discussion on the use of System IP for SoC design, one of ... » read more

Designing In The Rain
By Jon McDonald - 23 Aug, 2012 - Comments: 0

By Jon McDonald Recently I was running some errands on my motorcycle when I got caught in the rain. Living in Florida, this is a fairly common summer occurrence. Generally, as long as it’s not too much of a deluge, I can continue through to my destination and dry off when I arrive. I always get concerned looks from those going by in their enclosed vehicles—from some, “concerned” mig... » read more

Who Owns What And Why
By Ed Sperling - 23 Aug, 2012 - Comments: 0

Who’s calling the shots these days—and how long they’ll continue calling the shots—is turning out to be as much conjecture as playing the futures exchange. There are so many changes underway that even engineers are crossing boundaries no one ever expected and ending up in companies outside of IC design or moving from seemingly far afield into the design world. Still, there are some c... » read more

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models
By Various Writers - 23 Aug, 2012 - Comments: 0

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, TLMs have a number of advantages—they are available earlier, they allow usersto divide their focus on verifying functionality and protocol/timing details, they enable higher level reuse, and they... » read more

FPGA Design And Verification in Mechatronic Applications
By Various Writers - 23 Aug, 2012 - Comments: 0

The biggest challenge in using FPGA devices may be one of methodology. FPGA designers are familiar with HDL-based requirements-driven design methodologies for digital electronics. But how can requirements be expressed for a system that, while it contains digital elements, is fundamentally non-digital? Fortunately an executable HDL exists that extends the capabilities of the digital VHDL languag... » read more

Yikes! Why Is My SystemVerilog Testbench So Slooooow?
By Various Writers - 23 Aug, 2012 - Comments: 0

It turns out that [gettech id="31023" comment="SystemVerilog"] != [gettech id="31017" comment="verilog"]. OK, we all figured that out a few years ago as we started to build verification environments using [gettech id="31026" comment="IEEE 1800"] SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, ... » read more

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