category: System-Level Design

category: Auto, Security & Edge AI

Mixed-Signal IP Design Challenges In 28nm Process And Beyond
By Various Writers - 23 Aug, 2012 - Comments: 0

As process technologies continue to scale aggressively, it is becoming more challenging when developing high-quality, high-speed mixed-signal IP. Specifically, the 28-nm process poses some unique challenges not found in 65-nm and 40-nm technology processes. This paper discusses the low power requirements found in 28-nm processes and addresses issues associated with the aggressive scaling of ... » read more

Development of Complex Multicore Systems: Tracing Challenges and Concept (Part One)
By Various Writers - 23 Aug, 2012 - Comments: 0

This white paper is the first paper of a two-part Mentor Embedded multicore white paper series. In this paper, the challenges software developers face when developing, debugging, and validating software applications for a complex multicore system will be discussed. The paper also highlights some of the questions around hardware resource usage, tracing aids, tracing domains, and concepts for col... » read more

The Seven Layers Of Hardware-Software Debug
By Frank Schirrmeister - 22 Aug, 2012 - Comments: 0

By Frank Schirrmeister [caption id="attachment_9863" align="alignnone" width="639"] Seven Layers of Hardware/Software Debug[/caption] Of course I will be in trouble once this blog is posted. This post is about hardware/software debug,  and I tried to layer a set of different levels for the scope and applicability of debug. I counted seven layers, but I am sure that one may be able to arr... » read more

Experts At The Table: Coherency
By Ed Sperling - 17 Aug, 2012 - Comments: 0

System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: We’ve been hearing a lot about Wide I/O. Why is it so important and what effec... » read more

Experts At The Table: Coherency
By Ed Sperling - 17 Aug, 2012 - Comments: 0

System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: We’ve been hearing a lot about Wide I/O. Why is it so important and what effec... » read more

Experts at the Table: Stacking the Deck
By Ed Sperling - 10 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of Eda2Asic Consulting. ... » read more

Experts At The Table: Coherency
By Ed Sperling - 03 Aug, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: How do we bring software more in line with the hardware to impr... » read more

Experts At The Table: Coherency
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: What’s driving coherency and what sort of issues are you encou... » read more

Experts At The Table: Stacking The Deck
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler There is no doubt 3D stacking brings challenges not only from the design perspective, but also on the tool side. EDA vendors have been working for more than a few years to ready tools for stacked-die designs. How smooth the transition is, however, is a big question mark. Because the approach is new, not all the challenges are fully understood yet. And while most ED... » read more

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

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