category: System-Level Design

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IP That Makes IP Work
By Frank Ferro - 28 Jun, 2012 - Comments: 0

By Frank Ferro Just how important are IP subsystems to complex SoC designs? It appears much more than you may have thought just a few months ago. With the emergence of SoCs that now support the cloud computing revolution and every major cloud-connected device, SoC complexity is increasing at a dizzying pace. We commonly now see increasing number of IP cores, cores from multiple sources, di... » read more

Merger In Progress
By Jon McDonald - 28 Jun, 2012 - Comments: 0

By Jon McDonald June's been an interesting month, I was at the Design Automation Conference, DAC, in San Francisco, then a week later, the Freescale Technology Forum, FTF. DAC is generally more of a hardware design conference, while FTF generally is a bit more focused on software and systems. This year I was surprised at the similarities in some of the discussions at both shows. At DAC ther... » read more

All Indicators Point North
By Ed Sperling - 28 Jun, 2012 - Comments: 0

Designing and producing chips has always been difficult, but the number of things that conspire to make it harder at 20nm is the longest in the history of the semiconductor industry. The list will grow longer still at 14nm and beyond, not to mention so expensive that one mistake will kill a company. While system engineers and architects look at the challenges on the front end, the problems ... » read more

High Speed PCB Layout: Physical Design Issues Of Highspeed Interfaces
By Various Writers - 28 Jun, 2012 - Comments: 0

Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with very specific physical layout requirements that are not obvious. Unless you are thinking like an RF designer, there are many unexpected challenges to a successful high-speed layout. A ... » read more

PSL/SVA Assertions In SPICE
By Various Writers - 28 Jun, 2012 - Comments: 0

Assertion-based verification is a key aspect of any complete SoC or Silicon Realization flow. In this paper, we discuss how PSL (Property Specification Language)/SVA (System-V erilog Assertions) assertion semantics are extended for the first time to SPICE (Simulation Program with Integrated Circuit Emphasis)-level netlists and evaluated within a SPICE simulator, and present multiple examples an... » read more

Technical Considerations For Implementing USB 3.0 On SoCs
By Various Writers - 28 Jun, 2012 - Comments: 0

The Universal Serial Bus (USB) protocol has been the standard way to connect computers to external devices for nearly two decades. The protocol continues to evolve to support the growing demands of consumer devices. With its simplicity of use, USB is the number one choice of connectivity protocols in the consumer world. USB 3.0 early adoption began in 2010. Now, key USB software and systems pro... » read more

How Firm Is Firmware?
By Frank Schirrmeister - 26 Jun, 2012 - Comments: 0

By Frank Schirrmeister When blogging recently about Xilinx’s presentation at the Cadence DAC 2012 EDA360 theater, which was given by Dave Beal, I ran across the diagram he had used to outline the “development stack” from hardware to software. Dave had described a virtual prototype to the audience as a functional model that recreates the WHAT rather than the HOW, duplicating the result ... » read more

Atrenta Buys NextOp
By Ed Sperling - 20 Jun, 2012 - Comments: 0

By Ed Sperling Atrenta said today it will acquire NextOp Software, a formal tools startup that was created in 2006 and which came out of stealth mode in 2010. The move is interesting as much from a business perspective—it pits Atrenta against Jasper Design Automation, at least in the narrow assertion synthesis and assertion generation markets—as what it says about the increasing interes... » read more

Executive Briefing: Trillion-Gate Designs
By Ed Sperling - 31 May, 2012 - Comments: 0

Wally Rhines, CEO of Mentor Graphics, talks with System-Level Design about what's needed for trillion-gate designs, the increasing demands of verification and emulation, new tools for stacked die and the trend toward designing for the enterprise. [youtube vid=pQs1qNkFvVo] » read more

Executive Briefing: Orchestrating Change In IC Design
By Ed Sperling - 31 May, 2012 - Comments: 0

Cadence CEO Lip-Bu Tan sounds off to System-Level Design about what's changing in EDA, in Cadence, in the supply chain, and the need to make it all work together. [youtube vid=iwl5HOs4UsU] » read more

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