category: System-Level Design

category: Auto, Security & Edge AI

ESL Requires New Approaches To Design And Verification
By Ann Mutschler - 22 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As more data gets front loaded into SoC architectures today, understanding verification challenges as well as communication between the front and back end has never been more critical. “All of this is getting more complicated,” said John Ford, director of marketing at ARM. “There was a time when an ARM processor core was all that was on a chip. Now there’s ... » read more

New Standards For Connectivity
By Ed Sperling - 22 Jul, 2010 - Comments: 0

By Pallab Chatterjee The last couple of months have been busy for data transfer standards. Consider the following moves: Power Line Communication (PLC) has become a new standard by the IEEE and has two groups promoting it: HD-PLC and Home Plug Alliance. Bluetooth also has made progress with the draft of the new Bluetooth Low Energy Technology as part of the July version 4 specificatio... » read more

‘Good’ Vs. ‘Good Enough’
By Ed Sperling - 22 Jul, 2010 - Comments: 0

By Ed Sperling The decision for when a chip is ready for tapeout is changing—both in time and sometimes in terms of who’s actually making that decision—as the amount of software being developed by hardware companies continues to grow. At the root of this shift are two very different concepts about what constitutes a market-ready product. For SoC engineers, fixing bugs after a chip has... » read more

The Upside Of Glitches
By Ed Sperling - 22 Jul, 2010 - Comments: 0

There has always been a struggle between the verification and marketing sides of any chip company. The solution in the past has simply been to hire lots more verification engineers on a contract basis prior to tapeout and to muscle through the debug process. Creating a more generic platform and differentiating it with software changes that equation, and that is raising lots of concern behind... » read more

Misuse Of Thermal Numbers
By Javier DeLaCruz - 22 Jul, 2010 - Comments: 0

By Javier DeLaCruz So many of us in the semiconductors realm are guilty of using JEDEC thermal data incorrectly. I often get questions such as “how much power can this package handle” or “what’s the thermal efficiency of this package.” Unfortunately, in almost all situations these questions cannot be generally answered. The numbers we throw around for thermal performance come fr... » read more

Smarter Video Chips, Smarter Business Model
By Ed Sperling - 21 Jul, 2010 - Comments: 0

Pixim's CEO talks about what the company outsources, what it keeps internal, and how it differentiates from the competition. [youtube vid=jDoaQ91QM3c] » read more

The Changing Supply Chain
By Various Writers - 14 Jul, 2010 - Comments: 0

By Kalar Rajendiran In efforts to improve product quality AND cut development and production costs while decreasing time to market, fabless semiconductor companies (FSCs) and OEMs have outsourced functions that didn’t add value to their products and to the company’s bottom line. Over the past 20+ years, they’ve outsourced EDA tools, test and packaging, IP core development and of course... » read more

Behind The Scenes
By Ed Sperling - 01 Jul, 2010 - Comments: 0

This year’s DAC should be one of the more interesting shows in several years, although not for the usual reasons. As an industry, we are just emerging from one of the worst downturns in decades. It started in December 2007, and various segments of the overall economy will begin picking up at different times, depending upon whether they’re leading indicators or trailing indicators. Netb... » read more

End User Report: EDA Industry Realignment
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, ... » read more

Design For Variability
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling Faced with shrinking margins, manufacturing process fluctuations that could mean one more or one less atom in a transistor and proximity issues in layout the most advanced chipmakers have begun designing for variability. Rather than working with fixed numbers, such as voltage, power and area, the goal of DFV is basically averaging all of these numbers. While this includes som... » read more

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