category: System-Level Design

category: Auto, Security & Edge AI

Connecting The Pieces
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qual... » read more

AMS Reference Flow 1.0: Ready For Prime Time?
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Pallab Chatterjee TSMC recently announced a game-changing flow for 32nm/28nm Analog Mixed Signal (AMS) design. The AMS flow 1.0 includes tools from multiple vendors that are sequenced to take a design from concept and device creation all the way to release to being included as IP in an SoC. The flow that is being offered is a departure from traditional custom analog and custom AMS design. ... » read more

Stressing Over 3D
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By David Lammers Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanic... » read more

The Future Of IP
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP. In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exac... » read more

Redefining ‘Good Enough’
By Ed Sperling - 24 Jun, 2010 - Comments: 0

The increasing amount of software content in devices and the ability to add fixes after tapeout is changing the definition of what’s considered a market-ready product. This is business as usual in the software world, where patches upon patches are considered routine. Service packs are a way of fixing problems when millions of lines of code interact with millions more lines of code in unan... » read more

Synopsys Plus Virage: Combinatorics Or Common Sense?
By Jack Harding - 24 Jun, 2010 - Comments: 0

By Jack Harding It should be no surprise. The industry has been consolidating and expanding and consolidating for nearly 40 years. So when Virage Logic was gobbled up by Synopsys and Denali was ingested by Cadence, it is really a lot more of the same. Or is it? There is a difference. Synopsys has made it crystal clear that its definition of EDA now permanently includes IP. Not that acquirin... » read more

The Road To DAC: One-On-One With Aart de Geus
By Ed Sperling - 11 Jun, 2010 - Comments: 0

Synopsys CEO Aart De Geus sounds off about the future of design and where growth will come from in the EDA market.   [youtube vid=GO-9ILL9fDg] » read more

The Road To DAC: One On One With Lip-Bu Tan
By Ed Sperling - 04 Jun, 2010 - Comments: 0

A look at what's driving Cadence's new EDA 360 strategy, the problem areas in EDA and why the company decided to buy Denali. [youtube vid=zreEWGsCe5A] » read more

The Great Divide
By Ed Sperling - 27 May, 2010 - Comments: 0

By Ed Sperling One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers. While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significan... » read more

TLM 2.0: Necessary for Co-Simulation
By Ann Mutschler - 27 May, 2010 - Comments: 0

By Ann Steffora Mutschler Transaction-level modeling – an abstracted representation of design IP above the RT level -- continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The TLM-2.0 standard is the current industry standard for creating interoperable transaction-level models an... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy