The Demise Of Static Timing Verification?


The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

Making The Most of Test Resources


Semiconductor testing is undergoing multiple paradigm changes at once with the common goals of producing more known good die per month with low test cost. Achieving these goals requires a delicate balance between yield, quality, and test times. There are multiple ways to go about making better use of existing resources, many of which involve an increasing use of design for test (DFT) methods... » read more

The Hidden Cost Of Contact Resistance


Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it's staring them in the face. For years, it could be managed quietly with routine probe card cleaning or a scheduled socket swap. That approach worked well enough when pin counts were lower and devices pulled less current, but the ground has shifted since then. Today’s AI processors m... » read more

Infusing Trust Into The Supply Chain


An expanding supply chain of dies feeding multi-die products is prompting chipmakers to reassess and expand on ways to instill trust from end to end. This reaches deeper than just connecting disparate data. It requires integrating complex systems across vendors and protecting vendor data while instilling confidence in their customers and partners. Yet despite the time and effort that has bee... » read more

6G Line-Of-Sight Repeaters, Dots, And Reflections


6G will open the door to ultra-reliable, low-latency communications, extended broadband, and machine communications, but its rapid signal attenuation places some sharp limits on where and how it can be used, and requires some expensive options to overcome those limitations. Applications include lifelike virtual reality for home and work use, highly interactive smart homes and cities, and aut... » read more

Cloud vs. Edge Gaming: Performance Gap Is Shrinking


Chip designers and gaming companies are scrambling to figure out whether the gaming market will tilt toward the cloud, the edge, or some combination of both. Multi-gigabit internet allows more people to play high-end games in the cloud, but edge-based gaming consoles and devices remain well-rooted, more secure, and private. Which one wins? So far, there are more questions than answers. Handh... » read more

Security Requirements And Penalties Grow For Chipmakers


Governments and systems companies are fundamentally changing the rules around semiconductor security, forcing chipmakers and their suppliers to comply with tough new regulations that require resiliency in hardware. Unlike in the past, chips and systems deployed in these markets must be able to respond to threats rather than waiting for the next version of a chip or IP to address vulnerabilities... » read more

AI’s Value In Chip Design Depends On Data Availability


Experts at the Table: Semiconductor Engineering sat down to discuss the advantages and challenges in using AI in designing chips, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir ... » read more

Government Funding For Chip Design Tools Spreads


Governments around the globe are starting to invest more heavily in chip design tools and related research as part of an effort to boost on-shore chip production, opening new opportunities for startups and established EDA companies. Those cash infusions, which are being doled out in the U.S., Europe, and Asia, are part of a growing recognition of the importance of design automation tools wit... » read more

Silicon Lifecycle Management Gains Traction, But It’s Complicated


Silicon lifecycle management (SLM) is gaining ground in semiconductor design and test by leveraging specialized on-die sensors and analytics engines to improve power, performance, yield, and reliability. Most modern SoCs mitigate the guesswork by leveraging DFT, which includes adding memory built-in self-test (BiST) or improving functional coverage, but these tests were meant for verifying c... » read more

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