category: Top Stories

category: Auto, Security & Edge AI

Multi-Modal AI In EDA Development Flows
By Brian Bailey - 31 Jul, 2025 - Comments: 0

RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

How AI Will Impact Chip Design And Designers
By Ed Sperling - 31 Jul, 2025 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the role and impact of AI in chip design with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir Arora, head of engineering... » read more

When Standards Enable Chiplets
By Brian Bailey - 30 Jul, 2025 - Comments: 0

Semiconductor Engineering sat down and discussed the need for standards to enable an ecosystem for chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute Solutions Group; and Rob Kr... » read more

On-Die And In-Package Interconnects: eBook
By Bryon Moyer - 28 Jul, 2025 - Comments: 0

We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

The Rise Of Panel-Level Packaging
By Laura Peters - 24 Jul, 2025 - Comments: 0

An insatiable demand for logic to memory integration for AI and high-performance computing is driving progress toward very large-format packages, which are expected to approach 10 times the maximum reticle size in the next few years. These assemblies are best developed using fan-out panel-level packaging, replacing today’s wafer carrier with a panel. Fan-out packaging enables substantially... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era
By Gregory Haley - 24 Jul, 2025 - Comments: 0

The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

Machine Learning Tools Help Bridge Design-To-Manufacturing Gap
By Katherine Derbyshire - 24 Jul, 2025 - Comments: 0

More aggressive feature scaling and increasingly complex transistor structures are driving a steady increase in process complexity, increasing the risk that a specified pattern may not be manufacturable with an acceptable yield. A single layer now requires more process steps, and each of those entails more tunable parameters than ever before. To help manage design risk, foundries provide det... » read more

Chiplet Ecosystem Slowly Emerges
By Brian Bailey - 23 Jul, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute S... » read more

Crisis Ahead: Power Consumption In AI Data Centers
By Ed Sperling - 21 Jul, 2025 - Comments: 2

AI data centers are consuming energy at roughly four times the rate that more electricity is being added to grids, setting the stage for fundamental shifts in where power is generated, where AI data centers are built, and much more efficient system, chip, and software architectures. The numbers are particularly striking for the United States and China, which are in a race to ramp up AI data ... » read more

Can Today’s Processor Architectures Be More Efficient?
By Bryon Moyer - 17 Jul, 2025 - Comments: 3

For years, processors focused on performance, and that performance had little accountability to anything else. Performance still matters, but now it must be accountable to power. If small gains in performance result in disproportionate power gains, designers may need to discard such improvements in favor of more power-efficient ones. Although current architectures undergo a steady cadence of... » read more

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