category: Top Stories

category: Auto, Security & Edge AI

Blurring The Lines On Prototyping
By Ann Mutschler - 23 Apr, 2015 - Comments: 0

Prototyping is an integral part of every [getkc id="81" kc_name="SoC"] today, with two main approaches being used: virtual or software-based, and physical, which includes FPGA-based boards as well as hardware emulation systems. [getkc id="104" kc_name="Virtual prototyping"] is typically used for software development in the early stages of SoC design, even before SoC [getkc id="49" kc_name="R... » read more

Sponges, Skyscrapers, And Low-K
By Katherine Derbyshire - 20 Apr, 2015 - Comments: 1

A sponge is a porous structure. So is a skyscraper. These two very different images exemplify the materials being considered for advanced low dielectric constant (κ) materials. Most porous dielectrics that have been tested up to this point resemble sponges. As Intel’s David Michalak explained at this month's Materials Research Society (MRS) Spring Meeting, these materials consist of a ba... » read more

New Patterning Paradigm?
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chip scaling is becoming more difficult at each process node, but the industry continues to find new and innovative ways to solve the problems at every turn. And so chipmakers continue to march down the various process nodes. But the question is for how much longer? In fact, at 16nm/14nm and beyond, chipmakers are finding new and different challenges, which, in turn, could slow IC scaling or br... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 16 Apr, 2015 - Comments: 1

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

Next EUV Challenge: Mask Inspection
By Mark LaPedus - 16 Apr, 2015 - Comments: 2

Extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography is still not ready for prime time, but the technology finally is moving in the right direction. The EUV light source, for example, is making progress after years of delays and setbacks. Now, amid a possible breakthrough in EUV, the industry is revisiting a nagging issue and asking a simple question: How do you inspect EUV p... » read more

Flash Dance For Inspection And Metrology
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

FinFET Rollout Slower Than Expected
By Mark LaPedus - 16 Apr, 2015 - Comments: 1

The foundry business is heating up as some new and large players are entering the 16nm/14nm [getkc id="185" kc_name="finFET"] market. But foundry customers are taking longer than expected to migrate to finFETs amid some technical and cost issues. On the foundry front, [getentity id="22846" comment="Intel"] has been the sole player in finFETs for some time. But now, [getentity id="22865" ... » read more

Ecosystem Changes
By Ed Sperling - 15 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

One-On-One: Dark Servers
By Katherine Derbyshire - 14 Apr, 2015 - Comments: 1

Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. To... » read more

Stacked Die, Phase Two
By Ed Sperling - 09 Apr, 2015 - Comments: 0

The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

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