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category: Auto, Security & Edge AI

Approaching IP Quality From Many Angles
By Ann Mutschler - 17 Oct, 2013 - Comments: 0

As SoC design complexity has increased, semiconductor design IP and the industry around it has grown in its level of sophistication. This is great news for the users of that IP whose demands for quality, reliability and other deliverables have also been on the rise. Making sure users have what they need requires close collaboration between the semiconductor foundries, IP providers and of cou... » read more

Multi-Beam Begins To Shine
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

After years of R&D and promises, multi-beam electron-beam technology is delayed and late to the market. The technology requires more funding and work than previously thought. And generally, the skepticism is running high for the technology. Finally, however, there is a ray of hope, and some momentum, in multi-beam—at least on the photomask front. Seeking to accelerate its multi-beam te... » read more

Debate Heats Up Over Bigger Glass
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

For more than two decades, photomask makers have been talking about moving to a new and larger mask size, sometimes called “bigger glass” by the industry. Generally, the discussions about “bigger glass” have been all talk and no action. But now, some chipmakers are turning up the volume in the discussions and are pushing for a larger mask size. A larger mask size would require the ph... » read more

Executive Briefing: Getting Direct On Litho
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down and talked with David Lam, principal of the David Lam Group, an investment and advisory firm. Lam is also the chairman of Multibeam, a multi-beam equipment startup for direct-write lithography and other applications. He founded Lam Research in 1980 and left as an employee in 1985. He served on Lam Research’s board for five years after that. SE: Multibeam ... » read more

The Upside Of Through-Silicon Vias
By Katherine Derbyshire - 17 Oct, 2013 - Comments: 0

Through-silicon vias (TSVs) for 3D integration are superficially similar to damascene copper interconnects for integrated circuits. Both etch the via, into either silicon or a dielectric, line it with a barrier against copper diffusion, then deposit a seed layer prior to filling the via with copper using some form of aqueous deposition. In both processes, the integrity of the diffusion barrier ... » read more

Challenges Mount For EUV Masks
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

ASML Holding’s first production-worthy scanners for extreme ultraviolet (EUV) lithography are expected to ship this year, but there are still a number of challenges to bring the technology into high-volume manufacturing. As before, the three main challenges for EUV are the power sources, resists and photomasks. To date, the resists are making progress, while the EUV power sources remain a ... » read more

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 11 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of IP portfolio marketing at TS... » read more

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

Power Is A Global Issue
By Brian Bailey - 10 Oct, 2013 - Comments: 0

Power is now the No. 1 target in developing chips. In a keynote speech at the recent Cadence Verification Summit, James “Jim” Hogan—an EDA investor associated with companies such as Sonics, Nimbic, Solido, AutoESL, Altos and many others, and previously part of Cadence’s Telos venture arm—made the point that power is the big problem that needs to be solved. We all know that reducing... » read more

Transient Current Crunch
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

When Intel talks, people listen. So when Intel executive VP Dadi Perlmutter said in a keynote at ISSCC in 2012 that transient power noise was one of the most limiting aspects of the chip design process—and how the package and the board inductance are limiting how low they can take the supply voltage—it showed the gravity of the challenge of effectively managing transient power. Transient po... » read more

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