category: Top Stories

category: Auto, Security & Edge AI

Preparing For 3D IC Stacking
By Ed Sperling - 22 Jul, 2010 - Comments: 0

By David Lammers Through-silicon vias (TSVs) are in various stages of late development, but design and manufacturing challenges remain before companies can gain the full benefits of the third dimension. Two camps are pushing hard to introduce TSVs—the design community and the manufacturing equipment companies. The initial goal is to connect graphics memories to graphics processors in mobi... » read more

Why Open Source Matters
By Ann Mutschler - 22 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler A huge effort has been under way to create virtual prototypes that allow true hardware/software co-design, but there are still a number of pieces missing. One significant missing element is a full library of IP models to guide the process, and the solution could come from an unlikely place—open source developers. Today, ‘open source’ IP generally seems to be ... » read more

ESL Requires New Approaches To Design And Verification
By Ann Mutschler - 22 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As more data gets front loaded into SoC architectures today, understanding verification challenges as well as communication between the front and back end has never been more critical. “All of this is getting more complicated,” said John Ford, director of marketing at ARM. “There was a time when an ARM processor core was all that was on a chip. Now there’s ... » read more

New Standards For Connectivity
By Ed Sperling - 22 Jul, 2010 - Comments: 0

By Pallab Chatterjee The last couple of months have been busy for data transfer standards. Consider the following moves: Power Line Communication (PLC) has become a new standard by the IEEE and has two groups promoting it: HD-PLC and Home Plug Alliance. Bluetooth also has made progress with the draft of the new Bluetooth Low Energy Technology as part of the July version 4 specificatio... » read more

‘Good’ Vs. ‘Good Enough’
By Ed Sperling - 22 Jul, 2010 - Comments: 0

By Ed Sperling The decision for when a chip is ready for tapeout is changing—both in time and sometimes in terms of who’s actually making that decision—as the amount of software being developed by hardware companies continues to grow. At the root of this shift are two very different concepts about what constitutes a market-ready product. For SoC engineers, fixing bugs after a chip has... » read more

Mobile Gaming: The Next Power-Saving Frontier
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Pallab Chatterjee Mobile and handheld gaming platforms are gaining lots of attention these days, and from a low-power engineering standpoint it poses a challenge that dwarfs any game played on the devices. Unlike mobile phones, these handheld platforms don’t have the luxury of trading off between multiple operating modes to extend battery life. Even worse, they have to perform at the ... » read more

Getting Low-Power IP Integration Right
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler When it comes to integrating multivendor IP, power concerns dominate the challenges that engineers face. To get it right however, there are definitely questions that should be asked when considering which IP to use, along with techniques to manage power complexity. When choosing IP, the following points should be considered: How mature is the IP being sold? Has... » read more

The Power Of IP
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As the number of design starts goes down the corresponding complexity of SoCs has gone up—and continues to grow. Everyone is looking at the value they can bring to the table as increasing proportions of SoCs are either reused from pre-existing IP within the company designing the chip or brought in from outside. Because is economically impractical to start an SoC... » read more

EUV Focus Shifts To Affordability
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By David Lammers Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, ... » read more

Keeping Models In Sync
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ed Sperling Models and higher levels of abstraction have been hailed as the best choice for developing SoCs at advanced process nodes, but at 28nm and beyond even that approach is showing signs of stress. The number of models needed for a complex SoC has been growing at each new process node, which makes it much more difficult to keep them updated and in sync as the design progresses down t... » read more

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