category: Top Stories

category: Auto, Security & Edge AI

Best Practices In Team Building
By Ed Sperling - 26 Aug, 2010 - Comments: 0

By Ed Sperling Putting analog and digital engineers in the same room used to elicit strange looks and under-the-breath comments, but most companies have gotten beyond that stage. Now the question is how to pair them up effectively, get them all on the same team—sometimes even with software engineers thrown into the mix—while still getting a product out the door on time. This is easier s... » read more

What’s Next After DRAM?
By Ed Sperling - 26 Aug, 2010 - Comments: 0

By Pallab Chatterjee At the most recent Denali Memcon, there was a panel discussion and debate about the future of DRAM and possible successor technologies. The discussion was moderated by Cadence’s Steve Leibson and featured Bob Merritt of Convergent Semiconductor, Barry Hoberman of Crocus, Ed Doller of Micron and Marc Greenberg of Denali/Cadence. The topic of the discuss was based on t... » read more

The Growing Software Challenge: From Stacks To SMP
By Ann Mutschler - 26 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler Building a system now includes software, but defining the software stack is a mounting challenge for engineers. What used to be almost exclusively drivers now includes RTOSes and OSes, executable files, middleware, firmware, IP, embedded software and applications. With millions of different embedded products, all with different sets of software, it comes down to pr... » read more

Extending Moore’s Law
By Ann Mutschler - 26 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler For Moore’s Law to perpetuate, the materials used in semiconductor manufacturing must do their part to allow the scaling of devices to occur. Some of the latest include a carbonless film deposition technology for 20nm transistors and smaller, a plastic memory device and a material compound of silicon, copper, nickel and iron that researchers believe could lower manu... » read more

The Shape Of Things To Come
By Ed Sperling - 26 Aug, 2010 - Comments: 0

By David Lammers Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations. “This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech... » read more

Defining Power Intent
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler Designing power-sensitive SoCs has never been more challenging given the tremendous demand for power efficiency in applications ranging from smart phones to servers inside data centers. That makes describing the power control architecture of a chip through power intent essential. Specifically, explained Will Ruby, senior director of product engineering and applicat... » read more

Can IP Be Standardized In Low-Power Designs?
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler SoC designers are beginning to embrace low power formats UPF (IEEE P1801) and the Common Power Format (CPF) to express power intent, but are these efforts enough to create standardized IP in low power designs? Mike Brogley, IP and solutions product marketing manager at Actel, believes it is possible. “Yes, IP can be standardized, but the main driver in low-pow... » read more

New Low-Power Memory Interface Ahead
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Pallab Chatterjee The trend in consumer electronic devices is toward a multimedia-centric data flow, forcing changes in the memory interface needed to handle it. The increased compute resources needed for video signal processing, along with high-definition audio, used to be the exclusive domain of mainstream desktop computers and servers due to their access to memory and high data throug... » read more

Rethinking Models
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ed Sperling The move to future process nodes will require more than just new materials, better layouts and higher levels of abstraction. It also will require a fundamental re-thinking of how high-level architectural models are created and what’s included in them. While the Transaction-Level Modeling (TLM) 2.0 standard has provided significant improvements for everything from layout to ... » read more

One On One With South Korea’s CTO
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ed Sperling Chang-Gyu Hwang, national chief technology officer for South Korea, sat down with Low-Power Engineering to talk about the future trends in technology, global business and power. Prior to his current role, which was created by the Korean government in April, he ran the semiconductor business at Samsung, where he spent the last 20 years in top management positions. He also is the... » read more

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