category: Top Stories

category: Auto, Security & Edge AI

End User Report: EDA Industry Realignment
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, ... » read more

Design For Variability
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling Faced with shrinking margins, manufacturing process fluctuations that could mean one more or one less atom in a transistor and proximity issues in layout the most advanced chipmakers have begun designing for variability. Rather than working with fixed numbers, such as voltage, power and area, the goal of DFV is basically averaging all of these numbers. While this includes som... » read more

Connecting The Pieces
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qual... » read more

AMS Reference Flow 1.0: Ready For Prime Time?
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Pallab Chatterjee TSMC recently announced a game-changing flow for 32nm/28nm Analog Mixed Signal (AMS) design. The AMS flow 1.0 includes tools from multiple vendors that are sequenced to take a design from concept and device creation all the way to release to being included as IP in an SoC. The flow that is being offered is a departure from traditional custom analog and custom AMS design. ... » read more

Stressing Over 3D
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By David Lammers Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanic... » read more

The Future Of IP
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP. In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exac... » read more

Is Asynchronous Technology Ready For Prime Time?
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler As the quest grows to manage power in everything from the handheld smart phone to sensors for automotive applications and contactless payment cards, designers are getting hungry for new design techniques that allow them to hit yield targets within their power budgets. One such design technique is decidedly not new. In fact, the concept of asynchronous techno... » read more

Special Report: Using FPGAs For 3D Stacking
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic. Xilinx declined to com... » read more

Power Or Performance?
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Pallab Chatterjee Most microprocessors have shifted to new small geometry processes in order to be the most efficient at power and high performance. However there is always a trade-off between power, performance and area (PPA) for semiconductors, and this is especially relevant for processors. In the current design space, processors are created as general-purpose products, but they are gene... » read more

Synopsys To Buy Virage Logic
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Synopsys bought Virage Logic today for $289 million, extending its IP portfolio well beyond just standard I/O and PHY into memory, logic and processor cores. The move strengthens Synopsys’ position as an all-in-one powerhouse with IP that can fit into an integrated flow. “A big part of the value is providing building blocks that work through the SoC flow,” said Joac... » read more

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