category: Top Stories

category: Auto, Security & Edge AI

Corners Up, Margins Down
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Complexity, less room for error and concern over adding any extra wires or circuits into chips because it may boost power consumption or affect the thermal profile are making it more difficult to tackle all the corners on an SoC. The problem gets worse with mixed signal chips, where the corners are far less definable. And it gets even more complex when it comes to turning on ... » read more

Changing Opinions About Noise
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Brian Fuller On a sunny, warm May day in 2009, NIST researcher Jason Campbell took the stage at an IEEE event in Austin with a presentation that was sure cast a pall over the booming low-power semiconductor world. Campbell’s paper, written with Liangchun Yu, Kin Cheung, Jin Qin, John S. Suehle, A. Oates, Kuang Sheng, was entitled “Large Random Telegraph Noise in Sub-Threshold Opera... » read more

The Great Divide
By Ed Sperling - 27 May, 2010 - Comments: 0

By Ed Sperling One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers. While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significan... » read more

TLM 2.0: Necessary for Co-Simulation
By Ann Mutschler - 27 May, 2010 - Comments: 0

By Ann Steffora Mutschler Transaction-level modeling – an abstracted representation of design IP above the RT level -- continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The TLM-2.0 standard is the current industry standard for creating interoperable transaction-level models an... » read more

Balancing Quality, Cost And Locale
By Ann Mutschler - 27 May, 2010 - Comments: 0

By Ann Steffora Mutschler As more features are packed into a single SoC there are simply more time-critical decisions to make. Instead of holding up one chip of a six-chip chipset, a delay or error on one chip can stop the whole parade. That explains why one of the most vibrant parts of the business at big EDA companies these days is standard IP, and why most of the other commercial IP make... » read more

Unified Design Flows Require New Skill Sets
By Ed Sperling - 27 May, 2010 - Comments: 0

By Pallab Chatterjee With the release of the InRoute product from Mentor, three of the major EDA vendors now offer unified data model design flows that feature logic synthesis, physical synthesis, place and route, timing closure with high accuracy RC tools, and physical verification based on full process tools. These new tools were created to address the need for simultaneous Multi-Corner M... » read more

IP Integration Creates Challenges For Power
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Managing power when integrating IP is becoming a critical issue at advanced process nodes—and the problem is getting worse. For starters, static power leakage that occurs when the transistors are “off” gets worse at each node. On top of that, multiple states to minimize dynamic power leakage have pushed complexity even further. Throw in third-party IP from m... » read more

Changes (For The Better) In Muticore Technology
By Ed Sperling - 13 May, 2010 - Comments: 0

By Pallab Chatterjee Subtle but important changes are occurring in the multicore world, particularly in the power per function that is available from each core. Two trends are increasingly evident. First, there is a growing need for higher-bandwidth data transfer or multiple-function processing for existing data transfer levels. And second, there is a shift to low power or mobile implement... » read more

A Shock To The System
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ed Sperling Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them. What was once considered a sideshow in SoC development is becoming a central and critical issue at advanced nodes. The good... » read more

Making IP Tradeoffs For Power
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Power may be expensive, but just turning off sections of a chip, lowering the voltage or using low-power manufacturing processes have their own costs. Whether using power, or managing it, there is a price. As Brani Buric, executive vice president at Virage Logic says, “Power is not free.” But fortunately, other things in a design can be traded off in order to a... » read more

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