category: Top Stories

category: Auto, Security & Edge AI

AI Accelerators Usher In New Era For IC Test
By Laura Peters - 07 Apr, 2026 - Comments: 0

Key Takeaways The parallelism in AI accelerators enables low latency but complicates failure isolation. HBM can account for 50% of package cost, so known-good stack assurance is critical. DFT and test cooperate to solve final test, singulated die test, SLT, and in-system test for data centers. AI accelerators are used for everything from training large language models to mak... » read more

Untrusted Analog Components Add Risks For Critical Infrastructure
By Anne Meixner - 07 Apr, 2026 - Comments: 0

Key Takeaways New certificate-based solutions are necessary within fabs and packaging houses to deliver trusted semiconductors. Physical IDs bind the device to the certificate, but it needs to be immutable and unclonable. Extrinsic IDs are required for analog, mixed-signal, sensor ICs as well as discrete components. Rising concern over the source and destination of chips, an... » read more

Moving Electrons, Not Just Vehicles
By Liz Allan - 02 Apr, 2026 - Comments: 0

Key Takeaways: There are several ways to convert AC power from the grid to DC power in the system. Some degrade the battery faster than others. Battery management systems monitor cell voltage, current, and temperature, helping to estimate state of charge, health, and useful remaining life. A PMIC with a multi-level converter is the most efficient way to get power from the battery to ... » read more

IC Security Threats Spike With Quantum, AI, And Automotive
By Ann Mutschler - 02 Apr, 2026 - Comments: 0

Key Takeaways: The top challenge for the chip architect is building post‑quantum cryptography securely into real hardware from the start, not just selecting approved algorithms. Security must be treated as a core silicon architecture decision early on, especially for long‑lived, automotive, and multi‑vendor systems. Automotive cybersecurity now requires a holistic approach span... » read more

The One Bit Problem That Can Break a System
By Ann Mutschler - 02 Apr, 2026 - Comments: 2

Key Takeaways: Bit flipping is no longer a rare reliability issue but a systemic risk driven by shrinking process nodes, higher clock speeds, lower voltages, and radiation exposure, leading to silent data corruption and potential system failure. The same mechanisms that cause accidental bit flips can be deliberately exploited through techniques such as clock, voltage, laser, and rowhamm... » read more

AI’s Potential And Limitations In Chip Design
By Ed Sperling - 01 Apr, 2026 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the opportunities and challenges of using AI in chip design, with Thomas Andersen, vice president for AI & Machine Learning at Synopsys; Sridhar Boinapally, senior director of analog/mixed signal tools/flow at Intel; Alex Starr, corporate fellow at AMD; Stuart Oberman, vice president for GPU hardware engineering at Nvidia; ... » read more

Challenges In Scaling Chips To 2nm And Below
By Ed Sperling - 30 Mar, 2026 - Comments: 0

Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Memory Wall Gets Higher
By Brian Bailey - 26 Mar, 2026 - Comments: 1

Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

Data Boom Puts Pressure On NoCs, Fabrics
By Liz Allan - 26 Mar, 2026 - Comments: 0

Key Takeaways: NoC challenges, such as wiring congestion, timing closure, and performance, must be considered in tandem with topology and placement. Topologies can be customized to meet an application’s specific data flow needs, with a system containing multiple topologies to suit different data or zones. What is challenging for one type of system, such as an SoC, switch, or AI chi... » read more

AI Won’t Kill Verification IP, But It Will Redefine It
By Ann Mutschler - 26 Mar, 2026 - Comments: 0

Key Takeaways AI will enhance, not replace, verification IP by automating test generation and debug. Verification IP’s core value will increasingly lie in trust, accountability, and system-level realism, especially as designs become more complex, multi-die, and security-sensitive. AI shifts verification bottlenecks from execution to specification quality, raising expectations for c... » read more

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