Memory Test Challenges, Opportunities

The semiconductor capital equipment market is on fire, and the memory chip test equipment sector is no different. But it is getting much more difficult on the memory side.

Memory test vendors are contending with next-generation devices, such as 3D NAND flash memories, HBM2 chips, low-power double-data-rate DRAMs, graphics DRAMs, phase-change memories, magnetoresistive RAMs, and resistive RAMs, some of which present new technical challenges to testing with their advanced packaging.

The memory test equipment market was in the doldrums earlier in this decade, according to Risto Puhakka, president of VLSI Research. From 2011 to 2016, the worldwide market was generally between $450 million and $550 million per year, he said. For 2017, VLSI Research is estimating an increase of 42.5% for the memory test equipment market, from $470 million in 2016 to about $670 million this year.

Advantest and Teradyne dominate the memory test equipment market, with some competition from UniTest and other vendors based in South Korea, Puhakka noted. VLSI Research estimates Advantest sold $160 million in memory testers during 2016, while Teradyne’s sales in the market were $135 million and UniTest posted $95 million last year.

Teradyne reported 2016 revenue of about $1.37 billion in its Semiconductor Test unit, which represented 78% of the company’s $1.75 billion in total revenue last year. Semiconductor Test revenues were primarily driven by system-on-a-chip device testing in the mobile application processor market, the company said. Memory tester revenue was not broken out.

The Hybrid Memory Cube, originally developed by Micron Technology and later supported by the Hybrid Memory Cube Consortium, has struggled to compete with the rival High Bandwidth Memory specification and its HBM2 successor. Originally developed by Advanced Micro Devices with SK Hynix, HBM became a JEDEC industry standard four years ago. HBM2 was adopted by JEDEC in early 2016.

Fig. 1: HBM2 memory. Source: SK Hynix

With the Hybrid Memory Cube, “volumes are still rather small,” Puhakka said. “It’s more of a technology issue than a capacity issue.”

When it comes to 3D NAND flash memory devices, another chip-stacking technology, “there are two different things in play,” Puhakka observed. “You have a substantially better memory controller technology in the chip, so you can basically have a lot of software applications to manage the memory within the chip. On the other side, you need to test for the reliability and you need to test for the functionality. You have internal controllers that can reduce the amount of test you need, but then at the same time your bins are going up substantially. And you have some reliability issues to deal with the which were not there before. So, those are the issues we think is driving the test from that perspective.”

Not much is known about testing the 3D XPoint nonvolatile memory technology developed by Intel and Micron, he noted. Teradyne specializes in testing HBM/HBM2 memories, Puhakka added.

One trend VLSI Research sees in automated test equipment is a move toward internal development of testers at Intel, Micron, and other companies. “When you look at the test market, there is a block of market that is not there because it is not supplied by the merchant suppliers,” Puhakka said. “That’s why people like National Instruments and those guys are doing well, because you buy these components and you put them in a rack, build a test interface, and now you get your devices tested.”

In a related area, VLSI Research ranked the top five vendors in test and burn-in sockets for 2016. It is a $1 billion market expected to grow 12% this year. Yamaichi Electronics led the field with sales of more than $118 million last year. Enplas grew its sales by 32% from 2015 to $91 million. Trailing those two suppliers were ISC International/ISC Technology, Smiths Interconnect (formerly known as Smiths Connectors), and LEENO Industrial.

Advantest has made memory testing the core of its ATE line, offering multiple models in its IC Test Systems portfolio for different types of memory chips.

“For this particular segment, the test methodology is not that much different from what we call the 2D NAND that people have been testing before,” Ken Hanh Lai, director of memory marketing and business development at Advantest America, said about 3D NAND flash memory. “Except with the 3D NAND, the memory density is greatly increased. There’s really a push to get lower-cost test solutions. So we’re seeing that there’s a trend to push higher parallelism at package test. For example, right now, many people are moving toward the 768 devices in parallel. And there may be a push to get beyond that. Right now, 768 parallelism seems to be the limit due to limitation of component handlers in the market. But even that particular solution is getting too expensive. Test times for these devices with high densities are getting longer and longer. People are looking for a cheaper way of doing the similar type of test coverage, but for a cheaper cost. There’s also a trend moving toward testing in burn-in chambers, where you can test thousands of devices in parallel.”

Not much has changed at the wafer-sort level. Companies are still moving toward one-touchdown per wafer probing. However, due to the increased memory density of 3D NAND flash, there’s a need for the tester to perform faster memory redundancy analysis and fail bit upload for offline analysis in order to keep test time manageable.

NAND flash memories typically end up in a solid-state drive (SSD) or in an embedded storage device like eMMC, according to Lai. “We are seeing that eMMC is transitioning to the Universal Flash Storage (UFS) and PCIe BGA SSDs for faster performance in mobile applications, such as high-end smartphones,” he notes.

“From a final/package test point of view for UFS and PCIe BGA SSDs, we’re seeing that people are adopting system-level test strategy — testing the device as a storage system rather than individual NAND die and controller die,” he said. “These devices require a completely different type of test architecture. The standard memory tester that drives address and data patterns over parallel interfaces no longer works for these devices. Instead, these devices require a tester that could support the high-speed serial interfaces and protocols of UFS and PCIe. Preferably, the same tester would have the capability to support both device types. And there is a product we have available for supporting these test requirements.”

Testing nonvolatile memory testing, such as and phase-change memories like 3D XPoint, is similar to NAND and DRAM. “The trend has been to leverage the same testers as used for NAND and DRAM,” Lai noted. “There are some differences, though. The technologies require more power supplies with wider voltage ranges.”

In DRAM applications, the LPDDR4/5 memory chips are used in high-end smartphones, according to Jin Yokoyama, Advantest’s manager of the Memory/Storage Marketing & Business Development Department. HBM chips and GDDR4/5 memories “are booming for not only the gaming market, but also some other markets, like automotive, ADAS stuff,” he said.

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