Chip Industry’s Technical Paper Roundup: Nov. 1

Racetrack memory; bottoms up-arranging nanoscale particles on a silicon chip; side-channel vulnerabilities; area-selective deposition on nm scale patterns; photonic deep learning on the edge; automotive architectures; wafer-scale integration of 2D semiconductors; computing systems that mimic neurons; photonic RAM; in-flash bulk bitwise operations.

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New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Nanoparticle contact printing with interfacial engineering for deterministic integration into functional structures MIT
Three-dimensional racetrack memory devices designed from freestanding magnetic heterostructures Max Planck Institute of Microstructure Physics in Halle, Germany
Risky Translations: Securing TLBs against Timing Side Channels Ruhr University Bochum (Germany) and Cyber-Physical Systems of the German Research Center for Artificial Intelligence (DFKI)
Quantification of area-selective deposition on nanometer-scale patterns using Rutherford backscattering spectrometry IMEC and KU Leuven
Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory ETH Zurich, POSTECH, LIRMM/Univ. Montpellier/CNRS and Kyungpook National University
Delocalized photonic deep learning on the internet’s edge MIT and Nokia Corporation
Methodical Approach for Centralization Evaluation of Modern Automotive E/E Architectures University of Stuttgart and Daimler Truck AG
Electrical Programmable Multi-Level Non-volatile Photonic Random-Access Memory George Washington University, Optelligence, MIT, and the University of Central Florida
Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits Imec
An Artificial Neuron with a Leaky Fin-Shaped Field-Effect Transistor for a Highly Scalable Capacitive Neural Network KAIST (Korea Advanced Institute of Science and Technology)



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