Devices And Transistors For The Next 75 Years

The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1]

Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers, and hybrid bonding as enablers. Hybrid bonding will be used to combine devices but also disparate materials in stacked complementary FETs (CFETs).

Regarding the extension of DRAM technology, “A new configuration may be in store for next-generation DRAMs, 3D designs where the capacitor stretches laterally,” said Seok-Hee Lee, technology advisor at the Solidigm division of SK hynix and former CEO SK hynix. “Yes, a lot of people are working on it now because you can relax the capacitor constraint, you can form it in the horizontal direction. There are a lot of challenges still, but by working very hard for next five years, you will see 3D DRAM in some form.”

Lee was joined by Gosia Jurczak, managing director of global emerging memories at Lam Research; Tahir Ghani, senior fellow at Intel; Anton DeVilliers, R&D vice president and lithography patterning fellow at TEL; Serge Biesemans, senior vice president of semiconductor R&D at imec; David Gundlach, chief of NIST’s Nanoscale Device Characterization Division; Nirmal Ramaswamy, vice president of advanced and emerging memory at Micron; and Heike Riel, an IBM fellow. (The moderators emphasized the panelists were speaking as industry veterans, not on behalf of their respective companies. What follows are excerpts of that discussion, with some minor edits for clarity.)

Silicon still reigns
The industry is continually exploring new materials, but silicon CMOS is likely to remain strong for the foreseeable future. “The silicon channel is a well-established material system that we have in the transistor, which actually is very difficult to beat,” said Lam’s Jurczak. “I would like to go back in history 20 years when the silicon germanium channel was published for the first time with very clear mobility benefit in long channel transistors. Yet, we had to wait to 20 years to see silicon germanium channel in products. Another example is III-V materials. Again, we have seen huge benefits for electron mobility, and it was actually a very good candidate for NMOS transistors. Five years later, after publishing tons of papers on the study of III-V materials, the conclusion was that we don’t see this benefit when we go to short-channel transistors because mobility drops out, and then we get high variability.”

Silicon CMOS remains the most well-understood and proven material, despite some limitations. “With this history, when I look at the 2D candidates, I have doubts about how we’re going to do this within the next 10 to 20 years,” Jurczak said. “What we see today in mobility is that it’s actually not reaching what we can see in silicon.”

Still, there is a lot of optimism about stacking 2D materials and mobility will likely increase. “This is really a great option,” said IBM’s Riel. “With nanosheets, you see the stacking works, and it has fundamental advances in gate-all-around. The community is great at identifying the challenges and then working on them. We started more than 20 years ago with gate-all-around and now it’s here.”

“Devices made out of 2D materials for channel will need to be stacked,” said imec’s Biesemans. “It’s too hard to imagine placing nMOS-pMOS-nMOS-pMOS-…side by side as we do in planar or finFET technologies. 2D material devices should happen in stacked nMOS and pMOS tiers. To create that path, first stacked silicon should happen, then replace a channel material next. But the strain isn’t there. I somehow think the strain is missing.” He added that as hybrid bonding processes mature, they will become more commodity-like processes, eventually allowing implementation at the transistor level.

“Compared to non-stacked options, stacking will enable combinations of materials with different atomic lengths and different substrates,” said Intel’s Ghani.

Limits of DRAM, NAND
TEL’s DeVilliers noted that stacking and hybrid bonding are far from trivial. “Our friends in the memory world showed us how to stack,” he said. “It’s not hard to stack. It’s hard to stack and make money with it. A lot can be learned about stacking from 3D NAND from the tool side.”

Moving from the device to interconnect needs, Jurczak pointed to the need for lower thermal budgets and alternative materials. Panelists discussed the latest trend to backside power. Interconnecting frontside vias is getting harder, particularly patterning, overlay, and opening all vias as dimensions approach several nanometers.

NIST’s Gundlach, meanwhile, spoke about the need to maintain precision and accuracy in metrology. “Our ability to resolve things better and across a larger scale becomes really important,” he said. “Whereas ppm purity [of materials] might be sufficient at one point, perhaps we’re moving into ppb, which requires innovation in standard measurement services across the entire supply chain and lifecycle of the product.”

And Micron’s Ramaswamy focused on the extensibility of DRAM devices. “DRAM scaling is composed of a few pieces, and we can choose the piece that has a fundamental limit. Many of the features are getting below 10nm, and the contacts are even smaller. We can talk about a few tenths of a nanometer, or several dopant atoms. But typically, DRAM always has been about the capacitor, running an aspect ratio of about 50:1 and increasing, and dielectric constant of 40-plus. Can we get to 50 with not too much leakage? If I had to choose, I would say it’s the capacitor.”

SK hynix’s Lee agrees. “With the 1T-1C structure with geometric scaling, the capacitor is always a challenge. And if you look at the dielectric materials, you remember the conduction band offset versus the dielectric constant. You have this relationship. So yes, you can find a material other than zirconium oxide-based, but then you have less conduction band offset so that leakage current is less of an issue. But it’s always a change and  fundamentally, the capacitor is the limiter if I have to pick one.”

IEDM always has featured papers covering a variety of alternative memory architectures. Cache memory is an especially hot area. But the experts were asked whether any technology could replace the entrenched NAND and DRAM devices. “DRAM and NAND are so strong that they’re very difficult to beat,” said Jurczak. “So the future of DRAM is DRAM, but emerging memory may fill some gaps.”

And stacking capability with hybrid bonding may afford new uses for DRAM.

“With advanced packaging technology, some companies are already stacking SRAM on the CPU,” said Lee. “But beyond level 3, can we have level 4, an extra layer of cache? Depending on the workload, you may have benefits from this extra layer of cache.”

DRAM could fill that need. “Emerging memories have endurance issues, but it doesn’t have to be non-volatile memory, and the industry already has the ability to produce DRAM at large scale and use advanced packaging to connect it,” Lee said.

Intel’s Ghani agreed. “That definitely opens up a set of possibilities that were not available before,” he said. “Despite being off-chip, advanced packaging enables low off-chip latency and high bandwidth.”

Another topic of discussion was the move to near- or in-memory computing, particularly the return on investment for shortening the distance between memory and processing. “If we look at mobile computing, we lose about 15% of energy moving data on average,” Micron’s Ramaswamy said. “So for sustainability, power efficiency is very important. It’s a natural progression. It’s going to happen.”

But when is another matter. Ramaswamy noted that architects and programmers need to get together to show how near-memory/in-memory compute is going to work. He said that will take time to sort out.

EUV extensibility
EUV lithography was optional at 16/14nm, but at 7nm and below it is considered essential. But EUV already is running out of steam below 5nm, and leading-edge foundries — Samsung, Intel, TSMC — are looking ahead to high-NA (0.55) EUV and beyond. The big question is what comes after that? Will it be mask-free patterning or some form of self-assembly?

“In 2025, high-NA EUV will go into production,” said Intel’s Ghani. “Even with higher-NA EUV tools in the future, we may have to exercise pitch doubling or quadruple patterning schemes to enable continued dimensional scaling. But I don’t see a fundamental showstopper in the next six to eight years.”

Metrology is looking like more of barrier to advancing to the 1nm node and below, particularly with an increasing number of 3D structures. “Metric science has not kept pace with EUV,” said NIST’s Gundlach. “Can you do the measurements in a high-volume environment with EUV, or are we at the limit where we cannot see what we’re making? There’s a lot of opportunity there.”

Self-assembly does not appear to compete with existing patterning approaches, and multiple approaches may be used together and for different metal layers.

1,000-layer NAND
The transition from 200+ to 1,000 NAND layers is underway, but it will require new materials, NAND architectures, and improved capital equipment that can boost throughput.

“We are at 232 layers now and we will get to 1,000 layers, probably by end of the decade,” said Micron’s Ramaswamy. “We have a lot of these very critical etch and deposition and fill processes. We need an equipment roadmap to keep up with technology scaling. Right now we don’t have the ability to manufacture 1,000 layers. All processes need to be cost-effective, with the appropriate tolerances.”

Lee agreed. “We have to scale the stack because you cannot keep increasing the floors,” he said. “You also have to scale the ceiling, and high-aspect ratio etching is a big concern. Several years ago, in a different forum, I said if you deliver a tool that etches 12 wafers per hour, I have a problem. It’s actually getting worse. Engineers will find a solution.”

Quantum computing augments HPC
How quantum computing will be used in the future is another big unknown.

“Quantum is not here to replace the general CMOS transistor,” said IBM’s Riel. “This is not the intent of quantum computing. But quantum is here to solve mathematical problems that a classical digital computer can never solve. There are many examples, but we’ve almost forgotten them because we’ve learned a lot of approximations. In some cases they work well, but in other cases not so well. When we look closer, we see that quantum computing will help solve them.”

There has been steady improvement in quantum bit generation and coherence. “About three weeks back, the first processor with 433 qbits was announced, and we have clear targets of how we increase the performance concerning speed, scale and quality,” Riel said. “We know from the silicon industry that you need a clear roadmap, so I am very optimistic. We are at the start of something new that is not replacing the transistor, but is augmenting it.”

For quantum computing, this is a long time coming. Julius Edgar Lilienfeld conceived of a solid-state amplifier as far back as 1925, setting the stage for quantum devices, NIST’s Gundlach noted. “Recall the Lilienfeld patent was many decades ago, so the industry is quite good at having long-term visions and being able to deliver.”

Sustainability and talent go together
Two of the hot topics for the chip industry are attracting talent and improving sustainability, and the two are intertwined. Panelists agreed that young people care passionately about the health of the earth, so recruitment efforts need to better pitch the environmental impact they can make by working in the global semiconductor arena.

“We’re doing an interesting experiment where the big tool companies in Korea created a special program to guarantee jobs to university graduates,” said SK hynix’s Lee, pointing to the need for novel approaches. “If you are a professor, you have a strong opinion, because the mission is not just about getting jobs. Sustainability is a huge topic — net zero — and as a semi manufacturing company, there’s a lot of things we have to do. Regarding chemicals and gases, we’re still using greenhouse gases and working with materials suppliers to replace those. Semiconductor equipment consumes a lot of power, and we have to use renewable energy. For that, a company cannot do it without working with a lot of different parties, and many companies have signed up, so it’s going to happen.”

Still, this is a huge challenge, especially among certain chemicals and gases used in fabs. “The question is, ‘If we cannot replace gases, can we make abatement systems more efficient? Unfortunately, that typically means more power. We must optimize the full system, potentially consolidating abatement and consolidating pumps,” said Jurczak.

Micron’s Ramaswamy talked about three pillars in ESG (environmental, social, and governance) around water usage, hazardous waste generation, and disposal. “We’ve set very strong goals on sustainability — especially wastewater recycling, re-using up to 75% to 90%, and hazardous waste to landfill to zero. Getting fully renewable is a big one, too.”

In some respects, this is getting easier. “Awareness has been increasing over time, but we need to act in a way that is most effective,” said IBM’s Riel. “But some things, like saving energy, can be done right away.

For the semiconductor workforce, Jurczak emphasized the passion for technology that semiconductors inspire. “When I ask my colleagues why they are still in this industry, the most important reason they give is passion.”

Conclusion
Nearly 30% of the IEDM attendees were first timers. This is where the growth is, and it’s where the jobs will be in the future. The chip industry is entering an unprecedented era of innovation and growth, from device R&D to new materials and tighter integration. And the move to advanced packaging, with all the challenges that entails, will require new levels of cooperation to counteract the tapering off of Moore’s Law and the escalating cost of designing and fabricating chips.

A poll of audience members showed that the talent wall and cost wall pose the greatest barriers to continued semiconductor progress — well above perceived performance, power, and memory walls. But those walls are only temporary, and smart people equipped with a slew of new enabling technologies and materials will likely break all of them down — engineering new ways around them.

Reference
1. S. DeGendt and S. Datta (organizers), “75 Years of Transistor Technology – (No) Time for Retirement?” Dec. 6, 2022, IEEE International Electron Devices Meeting (IEDM).