EUV’s New Problem Areas

Extreme ultraviolet (EUV) lithography is moving closer to production, but problematic variations—also known as stochastic effects—are resurfacing and creating more challenges for the long-overdue technology.

GlobalFoundries, Intel, Samsung and TSMC hope to insert EUV lithography into production at 7nm and/or 5nm. But as before, EUV consists of several components that must come together before chipmakers can insert it. These include the scanner, power source, resists and masks. And more recently, the industry has begun sounding the alarm about stochastics, a phenomenon that involves random variations.

Some components are ready, while others are lagging. In fact, the EUV community for the first time has listed photoresists and related issues as the top challenge for EUV, surpassing the power source. After years of delays, the EUV power source finally meets the specifications for high-volume manufacturing (HVM).

The resists, which are light-sensitive polymers used to create patterns, are a different story and are among the culprits that cause stochastics. By definition, stochastics describe events that have random variables. They are unpredictable and without a stable pattern.

In the case of EUV, photons hit a resist and cause a reaction. But with EUV, there might be a new and different reaction during each event or multiple events. And so EUV is prone to events involving stochastics. Generally, the industry blames the resists for the stochastics, but variations also can occur with the photomasks and other parts of EUV.

Stochastics are not new. In fact, the phenomenon has haunted the EUV community for years. It is widely known that stochastics can cause variations in printed patterns. The industry has been working on the problem, but it either underestimated the issues, didn’t address them soon enough, or both.

What’s new is that the industry is finally coming to grips with another problem. A leading-edge logic chip incorporates a billion or more tiny contacts. If there is a mishap in the EUV process, the chip could suffer from stochastic-induced failures or defects. In other words, a chip can fail with a defect in just one contact.

It might be wishful thinking, but chipmakers believe they can dodge potential stochastic-induced defects at 7nm. In fact, EUV may happen at 7nm. But at 5nm or even 7nm, chipmakers may not be able to avoid these and other issues unless the industry comes up with some new breakthroughs. “It’s fair to say our industry is very optimistic about where we are heading for EUV lithography. We are poised for first-generation insertion into high-volume manufacturing,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries. “Looking ahead towards second-generation EUV lithography, resist stochastic effects are definitely one of the top concerns.”

Regardless of the nodes, EUV stochastics present headaches for chipmakers, fab tool vendors and the IC design community alike. “From a design point of view, the stochastic effects are truly random in that you can’t predict the location and amount of variation. Therefore, there is no systematic way to say that a particular layout feature should be modified in one area/placement of the layout verses another. In other words, there is no way to compensate for the effect during design other than avoiding all occurrences of sensitive features which translates into traditional design rule constraints,” said David Abercrombie, DFM program director at Mentor, a Siemens Business.

In response, the industry is taking steps to address some of the issues. Among them are:

• Vendors are improving the EUV resists.
• Applied Materials and ASML are developing a new class of e-beam metrology tools that promise to detect stochastic defects. Additionally, startup Fractilia has devised a way to help measure them.
• Then, with this new metrology data, chipmakers are asking competitive fab tool vendors to cooperate and help put the information together.

Why EUV?
Chipmakers need EUV because it’s becoming more difficult to pattern the tiny features using today’s lithographic techniques.

Initially, chipmakers will extend today’s 193nm immersion lithography and multiple patterning to 10nm and 7nm. These techniques work, but it’s becoming more challenging to use them for select features. So chipmakers initially hope to use EUV for the contacts and vias in devices. They will continue to use immersion/multi-patterning for the other portions.

To process contacts/vias, it requires two to four masks per layer for today’s processes at 7nm, according to GlobalFoundries. With EUV, though, it requires only one mask per layer.

The insertion of EUV depends on the readiness of the technology. Today, ASML is shipping its first production EUV scanner, the NXE:3400B. The 13.5nm wavelength tool has a 13nm resolution.

The EUV scanner can print fine features, but for years the EUV power source didn’t generate enough power. This impacted the overall throughput of the system. Now, ASML is shipping a 246-watt EUV power source, enabling a throughput of 125 wafers per hour (wph). This meets the HVM target levels.

The challenges are far from over, however. Today’s 193nm scanners can run non-stop at 250 wph. However, EUV uptimes hover around 70% and 80%. “We’ve showed that we can achieve the productivity numbers or throughput numbers,” said Michael Lercel, director of product marketing at ASML. “The focus this year is making sure we get the availability up. Our target is to get well above 90% availability.”

Additionally, EUV pellicles aren’t ready. “The pellicles are making progress. The transmission is still fairly low, but we’ve demonstrated that those pellicles can survive up to 245 watts. In off-line tests with some newer materials, we think they can even go above 300 watts,” Lercel said.

Counting photons
The resists are another challenge. For years, the industry has used chemically amplified resists (CARs) in 248nm and 193nm lithography.

In simple terms, a lithography light source generates photons or particles of light. The photons hit the CAR, generating an acid. Then, the CAR undergoes an acid catalyzed reaction during a post-exposure bake process.

CARs, which can be used for EUV, undergo a similar process with different results. “In the EUV case, it’s much more complicated and it’s really not well understood. You have a much higher energy photon,” said Gregory McIntyre, director of the Advanced Patterning Department at Imec. “It creates high-energy electrons that quickly cascade into lower energy electrons. Those electrons then interact with whatever they happen to bump in to. With this, there are quite a few unknowns, such as how many electrons are being generated and what are the energies—and more importantly, what kind of chemistries are resulting because of those electrons.”

Another way to explain the problem is the system exposes the resist to EUV light, sending a certain number of photons into the resist. Ideally, those photons would be evenly dispersed. But 10 photons might get absorbed into the resist in one spot, while in another location 8 photons are absorbed. This unwanted result is known as stochastics.

Fig. 1: Stochastic images. Source: Fractilia, GlobalFoundries, KLA-Tencor

Then, in another example, let’s say EUV light hits the resists in three consecutive and separate events. In the first event, the resist absorbs 10 photons. Then it absorbs 9 the next time, and 11 after that. The variability from one event to the next is a phenomenon called photon shot noise.

If one plots these events on a curve, the distribution of the photons is sometimes undesirable. “As we go to smaller and smaller feature sizes, what we find is that the Gaussian distribution starts to grow a tail and become asymmetric on one side. This growth of the tail leads to the increasing probability of highly unlikely events,” McIntyre said.

Fig. 2: Gaussian distribution with tails. Chart on right is based on 1B data points. Source: GlobalFoundries

Years ago, stochastics and shot noise were not on the radar screen, but the issues began to appear in 193nm lithography. In 193nm, chipmakers use a dose of 10mJ/cm² near the edge of a feature. “If I take a 1nm² area, then over the course of that exposure, 97 photons on average will pass through that area and go into the photoresist. But if I look at this larger volume of 10nm² on a side, I will have 9,700 photons on average,” explained Chris Mack, CTO of Fractilia.

So, with an ample number of photons to process a feature, the photon shot noise or variation amounts to only 1%, according to Mack.

In contrast, EUV photons have 14 times more energy per photon than 193nm light. “That means for the same dose, EUV has 14 times fewer photons,” he said. “So while in the example above, we had 97 photons exposing a 1nm² area, at EUV there are only 7 photons. The relative uncertainty is 1/square root of the number of photons. For 97 photons, that is a +/- 10% uncertainty. For 7 photons the uncertainty is +/- 40%.”

Compounding the problem is the fact that feature sizes are smaller at each node. You can count the number of photons in the process. At that point, the variations escalate exponentially.

This isn’t new. For years, Mack and others have warned that EUV stochastics can cause unwanted line-edge roughness (LER) in patterns. LER is defined as a deviation of a feature edge from an ideal shape.

LER can impact the performance of a transistor. In addition, LER doesn’t scale with the feature size, so it takes up a larger percentage of the pattern at each node.

Fig. 3: Line-edge roughness (LER). Source: Lithoguru, Fractilia

Besides LER, the industry is now worried about other parts of the chip, particularly the contacts. In operation an EUV scanner generates photons that pattern the contact holes. But at times, the process isn’t perfect, causing stochastic-induced defects in the contacts. Those defects show up as line breaks or holes that merge, sometimes referred to as “missing and kissing contacts.”

Fig. 4: Stochastic failures and shrinking process windows Source: Imec

These defects are catastrophic. “A contact hole is a little spot where you are going to put some photons. But if you only have a few photons, sometimes the contact hole gets 100 photons, sometimes it gets 80, and sometimes 140. The result is variation of the size of the contact holes,” Mack said.

These defects might crop up at 7nm, but they will likely surface at 5nm and beyond. “The stochastic effects in EUV essentially add a random variation over the normal dose/focus window in CD control as well as additional line-edge roughness and shot-to-shot dose variation. For the process guys this means less process window, which translates into larger DRC rules and less process shrink,” Mentor’s Abercrombie said.

“This makes design-oriented countermeasures very ineffective, as you can’t predict what will happen in any particular layout location or configuration and therefore not make some modification to counter it. In fact, since the stochastic effects can have positive and negative biasing and LER impacts around the targeted mean, any modification in a particular location could potentially hurt you as much as help you depending on what happened.” Abercrombie said. “Stochastic effects will primarily become significant contributors to decisions about which layers will use which litho/multi-patterning techniques to achieve the area and yield requirements needed to justify a process node.”

New solutions?
One way to solve the stochastic problem is to use a robust EUV resist. Ideally, chipmakers want a dose at 20mJ/cm². With a 250-watt source, this dose would achieve a throughput of 125 wph.

The 20mJ/cm² resists are not ready for 7nm—yet. 5nm is up in the air. So, the industry has made some compromises. At 7nm, chipmakers will use a CAR-type resist with dose at 30mJ/cm² to 40mJ/cm². These doses provide good resolution, but they are slower and impact the throughput of EUV. Chipmakers seem to get good yield with resists with doses between 30mJ/cm² and 40mJ/cm².

With a 30mJ/cm² dose, an EUV scanner with a 250-watt source has a throughput of about 104-105 wph without a pellicle, according to ASML. This is below the desired 125 wph target.

So what’s the solution in the future? One way is to boost the power source to 500 watts or 1,000 watts, suggested Yan Borodovsky, formerly a senior fellow at Intel. (Borodovsky recently retired from Intel). That way, you can use a higher dose and ensure yield. But 500-watt (or more) sources are still in R&D.

Another way is to improve the EUV resists. “Now that the power scaling is close to expectations, people have started to run more material,” said Richard Wise, technical managing director at LAM Research. “Once you look into the mechanism for defects or the stochastics defects, it is really driven by photon shot noise and resist blur. I can show a pattern, but the defects are catastrophic and I can’t yield.”

In EUV, there are two main resist types—CARs and metal-oxide. “CARs have a long history. The mechanism for that is well understood. The metal-oxides are newer,” Wise said. “Both systems are making progress. I would argue they are making progress at a similar rate.”

There are several variants of CARs. One candidate is a CAR with metal sensitizers. Metals have higher photo absorptions. “You can have a rather significant improvement in the behavior of CARs by putting in the right metal,” said Christopher Ober, a professor of materials engineering at Cornell.

Then, JSR, TEL and others are developing another variant called photo-sensitized CAR (PSCAR). For this, the mechanism releases an acid. Then, it triggers a photo-sensitizer. “Then, you can do a flood exposure and that leads to higher performance imaging,” Ober said.

Meanwhile, startup Irresistible Materials is developing a multi-trigger CAR. Besides CARs, Inpria is developing metal-oxide EUV resists, based on tin-oxide nanoclusters. “The theory on metal-oxide is sound. You capture more photons and there are higher densities for shot noise,” Lam’s Wise said.

Still, there are some challenges and trade-offs with resists. In a paper at SPIE, TEL and Imec compared CAR and metal-oxide resists at a low-exposure dose for a sub-36nm pitch. “You have litho, line CD and roughness in both cases,” said Sophie Thibaut, a process engineer at TEL, during a presentation at SPIE. “The CAR has a better LER and LWR performance in the mid- to high-frequency region. But the metal-containing resist is better for the low-frequency region.”

Fig. 5: CAR verses Metal-Oxide Resists Source: Imec

A billion contacts
Besides resists, the industry faces another challenge. How do you ensure good yield with a chip that incorporates a billion or more contacts?

Metrology, the science of measuring chips, is the first step. In the fab, chipmakers initially use a . But the CD-SEM is limited to 10,000 features per measurement, meaning it may be unable to detect all stochastic-induced defects.

“We need to measure many attributes from what you are looking at when you are dealing with EUV stochastics. You want to see the blocks, cuts and the right CD. You want to see that they are placed in the right place. And you want to see they are not touching the contacts and vias. You also want to see that you don’t have pitch walking,” said Ofer Adan, director of metrology and process control at Applied Materials. “You have EUV stochastics. They interact with the rest of the process steps. So we need to cover the interface between the EUV and non-EUV. (This includes) overlay and the mix-and-match between EUV and non-EUV, so it’s a big challenge.”

There are other challenges. “If you take the field size of the average scanner, and divide that by the pitch that we expect at these nodes for the contact holes, you approach about a trillion features per full field,” said Benjamin Bunday, senior member of the technical staff at GlobalFoundries. “We need to sample that with part-per-million-level sensitivities. How are we going to find that needle in the haystack? So in a sense, we are starting to close into a theory that we might want to measure a billion features in order to have good sampling and certainty of what’s there. Now, of course, I’m sure we’ll find a way to cut some corners and shave a couple of orders of magnitude off of that. We will have to, just to be practical. But that’s what the numbers are pointing at.”

To help solve the problem, Applied Materials and ASML are adding metrology capabilities to their e-beam inspection tools. They will incorporate CD-SEM and overlay capabilities to the mix.

In practice, a tool takes a shot of a large field of view in a short duration. Then, you use imaging tricks to enable a CD-SEM, providing millions of measurements in a few hours, according to equipment makers. “You can’t start solving those problems until you have the metrology that tells you what’s wrong,” ASML’s Lercel said. “If you can measure every single contact, you have this data that show you have these tails of the distribution.”

CD-SEMs and related tools can encounter signal-to-noise issues, causing a problem called CD bias. To solve that problem, Fractilia has a software tool capable of measuring LER and contact failures. The tool separates the errors of the CD-SEM and the lithographic features.

For EUV metrology, optical CD (OCD) is another possibility. Then, chipmakers must also locate the defects using wafer inspection tools, such as brightfield. “With EUV, the defects are more random, and that’s a big challenge,” said Neeraj Khanna, senior director of worldwide customer engagement at KLA-Tencor.

Once chipmakers gain insights into the metrology/inspection data, they can adjust the knobs on the fab tools to deal with EUV stochastics. It’s not that simple, however. “All of that requires more process control, and a lot of this comes back to basic yield control,” Khanna said. “If you’re controlling that only at one process step, such as litho, it’s going to be very difficult. Today, we have litho, etch or CMP and a very closed-loop feedback channel.”

As with any process, chipmakers must make the tools work together in the fab. But with EUV stochastics, chipmakers will likely encounter an explosion of new and complex data. ASML has one solution. “That’s a key part of this holistic lithography that we’ve added. (That is) making sure we have the metrology, making sure we have the right collaborations like with the etch companies, and making sure if we can get enough metrology data to do the right control loops. That’s what we think we need to pull together to make it successful,” ASML’s Lercel said. “If you can optimize all those parts together, you can actually end up achieving your edge placement error tolerances that you need.”

With so many different tools in the fab, that might not be enough. So chipmakers are asking their metrology and other tool suppliers to work together and help sort out the data. It’s unclear how that will work, as “there is no open framework to do this,” according to one chipmaker.

Still, the industry must cooperate. Otherwise, EUV insertion may become more difficult with even more stochastics to deal with.

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