tag: 3D-IC

Growth Spurred By Negatives
By Brian Bailey - 27 Jan, 2022 - Comments: 0

The success and health of the semiconductor industry is driven by the insatiable appetite for increasingly complex devices that impact every aspect of our lives. The number of design starts for the chips used in those devices drives the EDA industry. But at no point in history have there been as many market segments driving innovation as there are today. Moreover, there is no indication this... » read more

Three Technologies Enabling The Next Decade Of Hyperconnectivity
By Frank Schirrmeister - 27 Jan, 2022 - Comments: 0

As it has become a tradition in my 15 years of blogging, January is a month of both reflection and outlook. At the beginning of 2022, I am excited that key themes from 5 and 10 years ago—3D integration, artificial intelligence and machine learning (AI/ML), and ubiquitous needs for more connectivity driving 4G and 5G networks—clearly have exceeded expectations and forecasts from that time. L... » read more

High-Tech: Innovation At The Speed of Light
By Ansys - 12 Jan, 2022 - Comments: 0

As connectivity, digitalization, and autonomy proliferate, the boundaries between industries are blurring at an unprecedented pace. Promising to unleash $3TN in global technology market spending, the new competitive battleground is to be found where the system electronics and semiconductor worlds collide: The 3D Integrated Circuit System-on-a-Chip. Winning demands a new design paradigm that ... » read more

Setting Ground Rules For 3D-IC Designs
By Ed Sperling - 12 Jan, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance ... » read more

Expanding Advanced Packaging Production In The U.S.
By Mark LaPedus - 05 Jan, 2022 - Comments: 0

The United States is taking the first steps toward bringing larger-scale IC packaging production capabilities back to the U.S. as supply chain concerns and trade tensions grow. The U.S. is among the leaders in developing packages, especially new and advanced forms of the technology that promise to shake up the semiconductor landscape. And while the U.S. has several packaging vendors, North A... » read more

Industry Transforming In Ways Previously Unimaginable
By Brian Bailey - 30 Dec, 2021 - Comments: 0

Early in the year, everyone expected that the availability of COVID vaccines would signal the start of a return to normal, but that has certainly not been the case. Now the industry is taking a longer-term view about how to transform business, what is necessary for people to maintain their mental health, and how to create robust hybrid work environments for the future that do not discard the po... » read more

Challenges With Stacking Memory On Logic
By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Taking 2.5D/3DIC Physical Verification To The Next Level
By Siemens EDA - 21 Dec, 2021 - Comments: 0

As package designs evolve, so do verification requirements and challenges. Designers working on multi-die, multi-chiplet stacked configurations in 2.5/3D IC designs can use Calibre 3DSTACK physical verification checks to verify die alignments for proper connectivity and electrical behavior. The Calibre 3DSTACK precheck mode enables design teams to find and correct basic implementation mistakes ... » read more

Manufacturing Bits: Dec. 14
By Mark LaPedus - 14 Dec, 2021 - Comments: 0

3D-SOCs At this week’s IEEE International Electron Devices Meeting (IEDM), a plethora of companies, R&D organizations and universities presented papers on the latest and greatest technologies. One of the themes at IEDM is advanced packaging, a technology enables an IC vendor to boost the performance of a chip. Advanced forms of packaging also enables new 3D-like chip architectures. Fo... » read more

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