tag: ASIC

Clock Domain Crossings in the FPGA World
By Aldec - 30 Jan, 2019 - Comments: 0

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More import... » read more

Debug Tops Verification Tasks
By Ann Mutschler - 20 Dec, 2018 - Comments: 0

Verification engineers are spending an increased percentage of their time in debug — 44%, according to a recent survey by the Wilson Research Group. There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are be... » read more

Resets and Reset Domain Crossings in ASIC and FPGA designs
By Aldec - 28 Nov, 2018 - Comments: 0

This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To read more, click here. » read more

AI Chip Architectures Race To The Edge
By Kevin Fogarty - 28 Nov, 2018 - Comments: 0

As machine-learning apps start showing up in endpoint devices and along the network edge of the IoT, the accelerators that make AI possible may look more like FPGA and SoC modules than current data-center-bound chips from Intel or Nvidia. Artificial intelligence and machine learning need powerful chips for computing answers (inference) from large data sets (training). Most AI chips—both tr... » read more

Why Chips Die
By Brian Bailey - 12 Nov, 2018 - Comments: 4

Semiconductor devices contain hundreds of millions of transistors operating at extreme temperatures and in hostile environments, so it should come as no surprise that many of these devices fail to operate as expected or have a finite lifetime. Some devices never make it out of the lab and many others die in the fab. It is hoped that most devices released into products will survive until they be... » read more

5 Best Practices For Successfully Managing An ASIC Supply Chain
By DELTA, a part of FORCE Technology - 05 Nov, 2018 - Comments: 0

Managing an end-to-end ASIC supply chain is one of the primary challenges of chip projects. Not only is the process long and complex, but it involves multiple technologies, dependencies and stakeholders. In this paper, we've assembled five best practices to help you translate ASIC specifications into a final product through a smooth supply chain process, including: Avoid costly time-... » read more

Reduction In First Silicon Success
By Brian Bailey - 25 Oct, 2018 - Comments: 0

Every two years, Harry Foster, chief scientist for Mentor, a Siemens Business, works with Wilson Research to do a verification study. Those studies have influenced many in the industry, indicating where users are experiencing the most pain, spending their time, growing their team sizes and where money would be best spent. However, over the past four years, the ASIC industry has basically been i... » read more

Using ASICs For AI Inferencing
By Ed Sperling - 10 Oct, 2018 - Comments: 0

Flex Logix’s Cheng Wang looks at why ASICs are the best way to improve performance and optimize power and area for inferencing, and how to add flexibility into those designs to deal with constantly changing algorithms and data sets. https://youtu.be/XMHr7sz9JWQ » read more

Using High-Bandwidth Memory
By Ed Sperling - 01 Oct, 2018 - Comments: 0

eSilicon’s Tim Horel talks about HBM, what engineers need to know to work with this technology, and how it integrates with ASICs at advanced nodes. https://youtu.be/0Yq2XHGF6UE » read more

Achieving ASIC Timing Closure With Speedcore eFPGAs
By Achronix - 05 Sep, 2018 - Comments: 0

Achronix's Speedcore eFPGA IP allows companies to embed a programmable logic fabric in their ASICs, delivering to end users the capability to modify or upgrade the functionality of an ASIC after being deployed in the field. This flexibility dramatically expands the solution space that can be served by the ASIC as it can be updated to support changing standards and algorithms. Timing closure is ... » read more

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