tag: Cadence

Serial Wire Debug (SWD) Protocol: Efficient Debug Interface For Arm-Based Systems
By Divya Chawla - 12 Mar, 2026 - Comments: 0

Modern embedded systems are becoming increasingly compact, power efficient, and feature rich. As SoCs integrate more functionality, developers need reliable debug access without increasing pin count or board complexity. Serial Wire Debug (SWD) addresses these needs by providing a streamlined alternative to JTAG, enabling high performance debug features using only two pins, making it ideal for t... » read more

Scale Up, Scale Out Get a New Partner
By Bryon Moyer - 12 Mar, 2026 - Comments: 0

Key Takeaways: Three AI data center scaling strategies are scale-up, scale-out, and scale-across. Scale-up is within a rack; scale-out is between racks; scale-across is between data centers. Each of the three uses a different interconnect strategy to optimize either latency or jitter. As today’s data center workloads — especially for AI and HPC — outgrow the physical, ... » read more

Accelerating 4D Imaging Radar with Vision 4DR
By Cadence - 11 Mar, 2026 - Comments: 0

4D imaging radar enhances automotive sensing by adding elevation to traditional range, velocity, and azimuth measurements. This enables better target detection and classification, enabling safer driving decisions. Multiple input multiple output (MIMO) antenna technology has expanded the role of radar sensing from tracking moving targets to high-resolution imaging of the surroundings. High... » read more

Chip Industry Week In Review
By The SE Staff - 06 Mar, 2026 - Comments: 0

Think tank IAPS' report on AI integrity attacks contends that advanced AI systems must be protected from hidden tampering, backdoors, or unauthorized changes that could alter their behavior or outputs, especially when AI adoption is scaling rapidly, with over 60% of the federal workforce now using AI every day. Geopolitics The U.S. government has drafted new export rules that may give W... » read more

Auto Security Accelerates With Standardization And Certified Silicon
By Ann Mutschler - 05 Mar, 2026 - Comments: 0

Key Takeaways The automotive sector is actively developing and delivering secure parts and features ranging from secure boot to encrypted data and in-network protections. The cost of a breach can involve everything from ransomware to liability and/or damage to a brand. New standards are being introduced to ensure security, and technology developers are integrating cybersecurity requi... » read more

Limiting AI/ML Tools To Ensure Physical AI Safety, Security
By Liz Allan - 05 Mar, 2026 - Comments: 0

Key Takeaways: AI-based tools can help monitor physical AI systems and LLMs, but human oversight is still needed to avoid false positives, bias, and other anomalies. For autonomous vehicles and robots, edge case scenarios and understanding human values are weak points, especially as moral and social values change over time. AI tools are growing and becoming increasingly helpful for c... » read more

New Automotive Architectures Are Shaking Up Processor And Memory Choices
By Ann Mutschler - 05 Mar, 2026 - Comments: 0

Key Takeaways Assisted and autonomous driving require more data from more sensors, and much faster processing of some of that data. The shift to software-defined vehicles and centralized intelligence makes it easier to identify where the most advanced processors and memories are required, and where older and less expensive technologies can be deployed. Technologies that were largely ... » read more

Edge And Micro Data Centers: Powering The Real-Time Digital World
By Veena Parthan - 05 Mar, 2026 - Comments: 0

The modern world no longer runs on delayed responses. It runs on immediacy. When a self-driving vehicle identifies a pedestrian, when a factory robot adjusts production in milliseconds, or when an augmented reality overlay appears instantly during remote surgery, there is no tolerance for latency. These applications demand data processing that happens almost at the speed of human reflexes. B... » read more

Blog Review: Mar. 4
By Jesse Allen - 04 Mar, 2026 - Comments: 0

Cadence's Subash Peddu digs into the challenge of balancing performance, power efficiency, SoC layout optimization, and futureproofing when defining SoCs and memory subsystems for tomorrow’s AI accelerators. Siemens' Nicolae Tusinschi suggests that formal verification isn't just about finding bugs, and the ability to achieve mathematical certainty can fundamentally change how hardware desi... » read more

New Challenges In Signoff
By Ed Sperling - 03 Mar, 2026 - Comments: 0

Multi-die assemblies coupled with leading-edge process nodes make signoff increasingly challenging and scary. There are more corner cases and more data to consider, but no slack in the delivery schedule. Marc Heyberger, product engineer group director at Cadence Design Systems, talks about full-chip timing, flat versus hierarchical timing analysis, the ongoing development of full 3D-ICs, and wh... » read more

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