tag: EDA

PPA(V): Performance-Per-Watt Optimization With Variable Operating Voltage
By Synopsys - 10 Nov, 2021 - Comments: 0

Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform, uniquely built on a singular RTL... » read more

What’s Missing For Designing Chips At The System Level
By Ed Sperling - 01 Nov, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Dealing With Market Shifts
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Back in the days when I was in EDA development, I was taken in by the words of Clayton Christensen when he published "The Innovators Dilemma." He successfully introduced the technology world to the ideas of disruptive innovation. One of the key takeaways was that you should always be working to make your own successful products redundant, or someone else will do it for you. One tool I worked... » read more

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

EDA Vendors Widen Use Of AI
By Ed Sperling - 29 Sep, 2021 - Comments: 0

EDA vendors are widening the use of AI and machine learning to incorporate multiple tools, providing continuity and access to consistent data at multiple points in the semiconductor design flow. While gaps remain, early results from a number of EDA tools providers point to significant improvements in performance, power, and time to market. AI/ML has been deployed for some time in EDA. Still,... » read more

Optimization Driving Changes In Microarchitectures
By Ann Mutschler - 23 Sep, 2021 - Comments: 0

The semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of AI, and the need for differentiation and customization in leading-edge applications. In the past, much of this would have been accomplished by moving to the next process node. But with the benefits from scaling diminishing at each new node, the focus is s... » read more

Building Complex Chips That Last Longer
By Ed Sperling - 23 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Using ML In EDA
By Ed Sperling - 20 Sep, 2021 - Comments: 0

Machine learning is becoming essential for designing chips due to the growing volume of data stemming from increasing density and complexity. Nick Ni, director of product marketing for AI at Xilinx, examines why machine learning is gaining traction at advanced nodes, where it’s being used today and how it will be used in the future, how quality of results compare with and without ML, and what... » read more

A New Vision For Memory Chip Design And Verification
By Anand Thiruvengadam - 02 Sep, 2021 - Comments: 0

Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

Best Practices For Deploying Cliosoft SOS On AWS
By Cliosoft - 01 Sep, 2021 - Comments: 0

Semiconductor Integrated Circuits (ICs) are at the center of a number of modern technological innovations. To keep up with the ever-increasing pace of innovation, IC design teams require robust, scalable design management (DM) solutions to enable seamless global collaboration and increase productivity. This eBook outlines the advantages of, and best practices, for deploying Cliosoft SOS design ... » read more

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