tag: HBM

When The Test Cell Lies
By Gregory Haley - 07 Jul, 2026 - Comments: 0

Key Takeaways:   A marginal test result can be electrically valid and still diagnostically misleading because the socket, load board, and thermal loop are now part of the measurement.   Separating device drift from test-cell drift depends on tracking margins, variance, and calibration trends rather than bins alone.   In advanced packages, a false pass destroys value downstream, ... » read more

Data Center AI Growth Faces Challenging Bottlenecks
By Geoff Tate - 06 Jul, 2026 - Comments: 0

AI is rocketing ahead. It is the biggest industrial revolution of our age. AI adoption is growing, but still most are at early stages of learning. Anthropic, the leading frontier model provider with an annualized revenue run rate (ARR) of ~$47 billion with OpenAI close behind at ~$30 billion (Forbes). Google Gemini revenues aren’t broken out but Google Gemini processes over 3.2 quadrillion... » read more

Reducing Avoidable Memory Trips In HBM Systems
By André Bonnardot - 25 Jun, 2026 - Comments: 0

Picture a highway during rush hour. When a road has limited capacity, traffic backs up quickly because only so many cars can move through at once. Adding more lanes increases capacity, but it does not always guarantee a smoother commute. If cars keep flooding onto the highway, if exits are poorly placed, or if drivers have to stay on the road for long distances, congestion can still build. More... » read more

New USB Standards: Benefits And Incompatibilities
By Ed Sperling - 23 Jun, 2026 - Comments: 0

Just because it's a standard doesn't mean everything will work together, and this is especially evident with conflicting USB standards. David Shin, senior product marketing manager at Cadence Design Systems, explains where incompatibilities can crop up, why it's so difficult to control the different versions, and what's behind all this confusion. » read more

Will Your Chip’s Memory Work As Expected?
By Ed Sperling - 22 Jun, 2026 - Comments: 0

Increased density at advanced nodes, multi-die assemblies, and the rollout of AI everywhere are making it much more challenging to ensure that memory will function properly over its expected lifetime. Test is no longer about a single memory or one approach for testing memory. It can vary by application, by workload, and by architecture. Some testing is close to memory, some is built into memory... » read more

Google Details Five Generations Of TPU Training Supercomputers
By Technical Paper Link - 16 Jun, 2026 - Comments: 0

Researchers from Google and University of California, Berkeley published a technical paper titled “Google’s Training Supercomputers from TPU v2 to Ironwood: Architectural Stability, Scale, Resilience, Power Efficiency, and Sustainability Across Five Generations.” The paper summarizes five generations of Google TPUs, from TPU v2 through Ironwood, and examines how the systems evolved int... » read more

Enhancing High Bandwidth Memory (HBM) Reliability With 3D X-ray Inspection
By Chris Rand - 09 Jun, 2026 - Comments: 0

High Bandwidth Memory (HBM) is revolutionizing AI, high-performance computing, and advanced graphics systems. Its 3D architecture—stacked DRAM dies interconnected via through-silicon vias (TSVs)—delivers exceptional bandwidth and efficiency. But this complexity introduces new challenges for inspection and quality assurance. Why 3D X-ray for HBM? Traditional 2D X-ray imaging cannot fully v... » read more

Four-Tier Memory Hierarchy for LLM Reasoning (USC, UW)
By Technical Paper Link - 20 May, 2026 - Comments: 0

A new technical paper, "Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning," was published by researchers at USC and University of Wisconsin-Madison. Abstract "Reasoning LLMs produce thousands of chain-of-thought tokens whose KV cache must reside in scarce GPU HBM. The dominant response -- permanently evicting low-importance tokens -- is catastrophic for reasoni... » read more

Flash Getting Stacked High-Bandwidth Version
By Bryon Moyer - 14 May, 2026 - Comments: 1

Key takeaways: A new HBF 3D flash stack is similar to HBM for use in AI processing. HBF capacity will be much higher, allowing static storage of AI model weights, with optimized read speed. Samples are due out later this year, with accelerators featuring it coming out next year. AI inference using modern models requires billions of parameters, and moving them to where they c... » read more

AI Accelerator Testing Depends On DFT Innovations
By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

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