tag: Mentor Graphics

Transferring Skills Getting Harder
By Ed Sperling - 19 Jan, 2017 - Comments: 0

Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies. The result is that engineers are being forced to specialize, but when they work with other engineers with different ... » read more

FinFET And Multi-Patterning Aware Place-And-Route Implementation
By Mentor, a Siemens Business - 18 Jan, 2017 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Nitro-SoC place and route system handles them. To read more, click here. » read more

Blog Review: Jan. 18
By Jesse Allen - 18 Jan, 2017 - Comments: 0

Mentor's Michael White warns that while skipping a node can be appealing, be prepared for the increase in computation requirements. Synopsys' Hezi Saar checks out the benefits of moving to the MIPI I3C standardized sensor interface. Cadence's Paul McLellan highlights a talk by Eric Grosse on approaches to security and the RISC-V architecture. Applied's Mike Chudzik explains the problem... » read more

What Can Go Wrong In Automotive
By Ed Sperling - 17 Jan, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

Choosing Power-Saving Techniques
By Ann Mutschler - 16 Jan, 2017 - Comments: 1

Engineers have come up with a long list of ways to save power in chip and system designs, but there are few rules to determine which approaches work best for any given design. There is widespread confusion about what techniques should be used where, which IP or subsystem is best, and how everything should be packaged together. The choices include everything from the proper level of clock and... » read more

The Week In Review: Design
By Jesse Allen - 13 Jan, 2017 - Comments: 0

M&A Synopsys acquired another code analysis company, Forcheck. A privately held software company based in the Netherlands, it provided a static analysis tool for detecting coding defects and anomalies in Fortran applications. Forcheck technology will be integrated into the Coverity tool. Terms of the deal were not disclosed. IP & Specifications Cadence launched verification IP ... » read more

Finding Evasive System-Level Bugs Using Memory Consistency Algorithm
By Russell Klein - 12 Jan, 2017 - Comments: 0

Over Easter weekend in 2015 there was a jewelry heist at the safe deposit building at Hatton Gardens in London. The safe deposit vault was in the basement of a building and is used by jewelers in the area for storing large amounts of diamonds, jewelry, precious metals, and cash. The thieves made off with over $300 million in loot, making it the biggest heist in British history. For a while it l... » read more

Power State Switching Gets Tougher
By Ann Mutschler - 12 Jan, 2017 - Comments: 0

Power state switching delay is a key factor in minimizing power, and getting it right frequently means the difference between a successful design and a dead chip. But tradeoffs are intricate, complex and often involve judgment calls, making this a place where designs can go completely awry. For years, traditional, full-swing [gettech id="31093" comment="CMOS"] process technologies were used ... » read more

2017: Manufacturing And Markets
By Brian Bailey - 12 Jan, 2017 - Comments: 0

While the industry is busy chatting about the end of Moore's Law and a maturing of the semiconductor industry, the top minds of many companies are having none of it. A slowdown in one area is just an opportunity, in another and that is reflected in the predictions for this year. As in previous years, Semiconductor Engineering will look back on these predictions at the end of the year to see ... » read more

The Fundamental Power States For UPF Modeling And Power Aware Verification
By Mentor, a Siemens Business - 11 Jan, 2017 - Comments: 0

The IEEE 1801-2015 specifies the new semantics of power states through the ‘add_power_state’ UPF command. This new construct primarily allows incremental refinement of power states for power domains and its associated supply sets. The refinement concepts are actually originated from the fundamental conceptual set of power states termed as indefinite, definite, and deferred power states. In ... » read more

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