tag: Moore’s Law

3 Ways To Reload Moore’s Law
By Michael Watts - 18 Jun, 2015 - Comments: 1

The electronics revolution has been enabled because the cost and power per transistor has decreased 30% per year for the last 30 years — a fact usually associated with Moore's Law. This has been accomplished by simply reducing the transistor size while offsetting increased costs of equipment and mask levels, and by increased productivity from improved yield, throughput and wafer size. This... » read more

Managing Dynamic Power
By Ann Mutschler - 16 Jun, 2015 - Comments: 0

Working with finFETs is a study in contrasts. While leakage is now under control for the first time in several process generations due to the advent of different gate technology, dynamic power density caused by tightly packed transistors and higher clock speeds has become the big issue. “FinFET technology helps with reducing static/leakage power so when your logic is not active, you can sh... » read more

SoC Integration Headaches Grow
By Ed Sperling - 16 Jun, 2015 - Comments: 0

As the number of IP blocks grows, so do the headaches of integrating the various pieces and making sure they perform as planned within a prescribed power envelope. This is easier said than done, particularly at the most advanced process nodes. There are more blocks, more power domains, more states and use-model dependencies, and there is much more contention for memories. There are physical ... » read more

Big Data Needs Bigger Memory
By Kilopass - 04 Jun, 2015 - Comments: 0

By Rodrigo Liang Over the last few decades, the semiconductor industry has focused its considerable technical investments in accelerating software applications. Performance metrics for new semiconductor products are often correlated with their ability to lower the latency to access data required to run specific software applications. The need for increased performance from semiconductors ... » read more

What’s Different At 16/14nm?
By Ed Sperling - 28 May, 2015 - Comments: 0

Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

Executive Insight: Jack Harding
By Ed Sperling - 28 May, 2015 - Comments: 0

SE: What's changed over the past 12 months? Harding: My starting point these days is around consolidation. At last count there were about 85 companies in the semiconductor industry. My bet is that at this time next year there will be about 70. The size of deal will not matter. Nothing will be too big. The strategic question is whether you're playing musical chairs and when the music stops, ... » read more

How Semiconductor IP Became Critical To SoC Design
By Kilopass - 07 May, 2015 - Comments: 0

By Mark Templeton In 1991, I had the good fortune to be a member of the founding team of Artisan Components. We started the company believing that demand was about to appear for semiconductor intellectual property. We had a few data points. We knew that before a company could start a new chip project, they first had to design and verify all kinds of generic building blocks – things like ... » read more

Moore’s Law At 50
By Ed Sperling - 23 Apr, 2015 - Comments: 0

Moore's Law turned 50 this week…but not because of Gordon Moore. He observed that the number of transistors crammed onto a piece of silicon was doubling every 18 to 24 months and predicted that would continue to be the case. He was right, but it took many thousands of engineers who created methodologies and tools to automate the design and equipment to manufacture complex chips to make that o... » read more

What EDA’s Big 3 Think Now
By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

Pressure Builds To Revamp The Design Flow
By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

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