Blog Review: Mar. 4


Cadence's Subash Peddu digs into the challenge of balancing performance, power efficiency, SoC layout optimization, and futureproofing when defining SoCs and memory subsystems for tomorrow’s AI accelerators. Siemens' Nicolae Tusinschi suggests that formal verification isn't just about finding bugs, and the ability to achieve mathematical certainty can fundamentally change how hardware desi... » read more

Making Hybrid Bonding Better


Key Takeaways Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps preserve the Cu/dielectric during aggressive processes. The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipm... » read more

Chip Industry Week In Review


Big Deals and Fundings Rapidus secured US$1.7B in a new funding round from the Japanese government and the private sector to ramp 2nm production by next year. Open AI announced a $110B in new funding, with $30B from Nvidia, $30B from Softbank and $50B from Amazon. In a $100B multi-year deal, Meta will power its AI infrastructure with up to 6GW of AMD's GPUs. SambaNova and Intel ar... » read more

How IP Subsystems For Chiplets Will Unlock Your Next Wave Of Innovation


After many years of hope, promises, and commercial challenges, a robust environment that supports multi-die design is now taking shape. These events represent a sea of change for semiconductor design and manufacturing when compared to the traditional single-die monolithic design approach. Moore’s Law drove these original and substantial monolithic design accomplishments. But the massive requi... » read more

Using Data And AI More Effectively In EDA


Key Takeaways The data being produced by EDA tools tends to be for human consumption and has weak semantics. Agents are attempting to create actionable information from unstructured data. The Model Context Protocol may provide AI with access to better data. Semiconductor design generates a lot of data, but how much of that is useful or currently being used by AI tools? And h... » read more

AI Starting To Simplify Design Of Programmable Logic


Key Takeaways AI/ML and agentic tools are getting better at helping design and compile FPGAs, but downstream programming is slower to benefit. FPGAs historically have been designed using Verilog or VHDL, but higher-level languages could push more intelligence into compilers. ML tools can also help with mixed-signal co-design by automatically tuning DSP algorithms based on analog simu... » read more

What Designers Need to Know About UALink for Scalable AI Systems


As AI workloads rapidly scale, interconnect performance, latency, and memory access become critical bottlenecks. This white paper explores how the UALink protocol enables high-speed, low-latency, and secure GPU-to-GPU communication, unlocking scalable AI architectures beyond traditional limits. Key Takeaways: Learn how UALink enables efficient GPU memory pooling at scale Understand U... » read more

Blog Review: Feb. 25


Cadence's Mick Posner introduces the Foundational Chiplet System Architecture, a specification that aims to deliver a vendor and CPU-neutral architecture, common system partition guidelines, and a shared vocabulary and set of standards for system-level and interface definitions between chiplets. Synopsys' Scott Knowlton explains why LPDDR6 represents a big step forward in memory management c... » read more

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers


Key Takeaways Backside power delivery reduces routing congestion at the most advanced nodes and offers significant performance improvement options. But it also adds a bunch of new challenges involving via alignment and interconnects. Still, leading-edge foundries are making progress, and all of them plan to offer BPDNs at 2nm and below. Backside power delivery networks deliv... » read more

Chip Industry Week in Review


The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

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