IC Security Threats Spike With Quantum, AI, And Automotive


Key Takeaways: The top challenge for the chip architect is building post‑quantum cryptography securely into real hardware from the start, not just selecting approved algorithms. Security must be treated as a core silicon architecture decision early on, especially for long‑lived, automotive, and multi‑vendor systems. Automotive cybersecurity now requires a holistic approach span... » read more

The One Bit Problem That Can Break a System


Key Takeaways: Bit flipping is no longer a rare reliability issue but a systemic risk driven by shrinking process nodes, higher clock speeds, lower voltages, and radiation exposure, leading to silent data corruption and potential system failure. The same mechanisms that cause accidental bit flips can be deliberately exploited through techniques such as clock, voltage, laser, and rowhamm... » read more

Accelerating Automotive Innovation: SRAM Compiler Breakthroughs for 5nm and 3nm SoCs


Modern automotive SoCs must deliver extreme performance, functional safety, and long‑term reliability — all under growing power and thermal constraints. This white paper explains how next‑generation Synopsys SRAM Compiler IP for TSMC N5A and N3A helps design teams meet these challenges with measurable gains in PPA, reliability, and system robustness. Why Read this White Paper: See... » read more

Blog Review: April 1


Siemens EDA's Harry Foster considers why first-silicon success is continuing to decline even though tools are capable of handling much larger design sizes and identifies how increasingly complex interactions between components cause traditional verification assumptions to break down. Synopsys' Eldo N Baby explores dynamic voltage drop analysis, including how to bring in switching scenario in... » read more

AI’s Potential And Limitations In Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss the opportunities and challenges of using AI in chip design, with Thomas Andersen, vice president for AI & Machine Learning at Synopsys; Sridhar Boinapally, senior director of analog/mixed signal tools/flow at Intel; Alex Starr, corporate fellow at AMD; Stuart Oberman, vice president for GPU hardware engineering at Nvidia; ... » read more

Chip Industry Technical Paper Roundup: Mar. 31


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips 🔗 ETH Zurich, Rutgers University Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review 🔗 Univ... » read more

Challenges In Scaling Chips To 2nm And Below


Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Chip Industry Week In Review


Arm uncorked its first internally developed CPU chip this week, aimed squarely at the agentic AI data center market. Arm CEO Rene Haas (pictured) emphasized the CPU's power efficiency and performance/watt compared to other AI processor architectures. "We are obsessed with efficiency, and if you think about one of the biggest appeals that Arm has had over the years, it is power profile," he ... » read more

IP Requirements Evolve For 3D Multi-Die Designs


As Moore’s Law continues to slow and demand for compute density and bandwidth accelerates, the semiconductor industry is rapidly shifting from monolithic SoCs to 3D multi-die designs. While 2.5D integration has extended system scaling, it is no longer sufficient to meet the bandwidth, latency, and power requirements of AI, HPC, and advanced automotive applications. The move to true 3D multi-d... » read more

Memory Wall Gets Higher


Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

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