Edge, in-sensor AI processors; TMDC-based transistors; DRAM read disturbance threshold; replay-based validation for chiplets; LLM-specific algorithmic attacks; noise in tellurium transistors; FMEDA safety metrics; HW reverse engineering; slowdowns in multi-GPU LLM inference.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips 🔗 | ETH Zurich, Rutgers University |
| Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review 🔗 | University of Austria, ETH Zurich |
| Oxide induced degradation in MoS2 field-effect transistors 🔗 | imec, ETH Zurich |
| ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation 🔗 | Intel, Nvidia, Synopsys |
| Cascade: Composing Software-Hardware Attack Gadgets for Adversarial Threat Amplification in Compound AI Systems 🔗 | UT Austin, Intel Labs, Symmetry Systems, Microsoft, Georgia Tech |
| Revealing and Engineering Contact-Origin Noise in Ultrathin Tellurium Transistors 🔗 | POSTECH |
| Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification 🔗 | Robert Bosch GmbH |
| SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research 🔗 | Ruhr University Bochum, Max Planck Institute for Security and Privacy |
| Characterizing CPU-Induced Slowdowns in Multi-GPU LLM Inference 🔗 | Georgia Tech |
Find more semiconductor research papers here.
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