tag: Synopsys

Domain-Specific Design Drives EDA Changes
By Ann Mutschler - 03 Jan, 2022 - Comments: 0

The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

2021 Top Tech Videos
By Linda Christensen - 28 Dec, 2021 - Comments: 0

While the world’s chip shortage dominated the 2021 headlines, the semiconductor industry blazed new trails with the increased electrification of cars, focused AI applications, improving power/performance, better utilization of data deluges, dealing with design challenges in advanced nodes and much more focus on chip security. Semiconductor Engineering’s Tech Talks reflected these focus a... » read more

Batteries Take Center Stage
By Heidi Elliott - 27 Dec, 2021 - Comments: 0

For any mobile electronic device, the biggest limiting factors are the size, age, type, and utilization of the batteries. Battery technology is improving on multiple fronts. The batteries themselves are becoming more efficient. They are storing more energy per unit of area, and work is underway to provide faster charging and to increase the percentage of that energy that can be used, as well... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Dec, 2021 - Comments: 0

Deals Utilidata and Nvidia are teaming up on a software-defined smart grid chip that can be embedded in smart meters to with the aim of improving grid resiliency and integrating distributed energy resources (DERs) such as solar, storage, and electric vehicles. The U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) will test the software-defined smart grid chip as a way t... » read more

Reliability Concerns Shift Left Into Chip Design
By Ann Mutschler - 22 Dec, 2021 - Comments: 1

Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it's a way of offsetting rising design and manufacturing costs. What's changed is the new emphasis on solving these problems in the initial design. In the past, defectivity and yield were considered problems for the fab. Re... » read more

Challenges With Stacking Memory On Logic
By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

The Third Generation Of FPGA Prototyping
By Robert Parris - 22 Dec, 2021 - Comments: 0

Bench setups with physical prototypes lie at the very heart of electrical and electronic engineering. With all due respect to the many powerful forms of modeling and simulation, at some point the engineering team wants to work with hardware. When a system is built entirely from existing components, it is possible to build a prototype of the product as soon as it has been designed. When the desi... » read more

Blog Review: Dec. 21
By Jesse Allen - 21 Dec, 2021 - Comments: 0

Cadence's Paul McLellan points to Log4J, a logging utility with a new major vulnerability that could affect hundreds of millions of devices, what's being done to address it, and why the underlying problems may be around for decades. Siemens EDA's Ray Salemi continues explaining how to use Python for verification by checking out the Python logging module for pyuvm and how it compares to UVM r... » read more

Flexible USB4-Based Interface IP Solution For AI At The Edge
By Synopsys - 21 Dec, 2021 - Comments: 0

Consumers have become accustomed to smart devices that are powered by advances in artificial intelligence (AI). To expand the devices’ total addressable market, innovative device designers build edge AI accelerators and edge AI SoCs that support multiple use cases and integration options. This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP so... » read more

Perspectives On Why EUV Photomasks Are More Expensive
By Jan Willis - 20 Dec, 2021 - Comments: 0

There are fewer photomasks per wafer using EUV lithography, but each EUV photomask is more expensive. Given that, it’s not a surprise that a majority (74%) of industry luminaries surveyed in July say that EUV photomasks will contribute to an increase in photomask revenues for 2021 as shown in figure 1. In a 20-minute video, a panel of experts share their perspectives on what drives EUV photom... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy