tag: Synopsys

Always On, Always At Risk
By Ed Sperling - 18 Aug, 2021 - Comments: 0

Always-on devices are everywhere, and each of them is a potential target for hackers. While many people associate always-on devices with smart speakers such as an Amazon Alexa or Google Home, or a connected security camera, that's only one component in a system. There's a broader infrastructure behind those devices. So even if you power down a digital assistant/smart speaker, everything it's... » read more

Blog Review: Aug. 18
By Jesse Allen - 18 Aug, 2021 - Comments: 0

Arm's Charlotte Christopherson explores the possibilities of flexible, non-silicon electronics with the creation of PlasticArm, an ultra-minimalist Cortex-M0-based SoC that, even with just 128 bytes of RAM and 456 bytes of ROM, is twelve times more complex than previous flexible electronics. Cadence's Claire Ying highlights the importance of integrity and data encryption (IDE) technology for... » read more

Impact Of GAA Transistors At 3/2nm
By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Aug, 2021 - Comments: 0

Mobix Labs finalized its acquisition of Cosemi Technologies, a provider of hybrid active optical cables, optical transceivers, and optical engines. Mobix Labs provides wireless connectivity solutions with CMOS-based mmWave beamformers, antenna solutions, and RF semiconductors. “Our Cosemi acquisition bridges the gap between wireless and wired applications, enabling Mobix Labs to bring a full ... » read more

Time To Rethink Memory Chip Design And Verification
By Anand Thiruvengadam - 12 Aug, 2021 - Comments: 1

It’s no secret to anyone that semiconductor development grows more challenging all the time. Each new process technology node packs more transistors into each die, creating more electrical issues and making heat dissipation harder. Floorplanning, logic synthesis, place and route, timing analysis, electrical analysis, and functional verification stretch electronic design automation (EDA) tools... » read more

Lowering Energy Per Bit
By Ann Mutschler - 12 Aug, 2021 - Comments: 0

Energy is emerging as a focal point in chip and system design, but solving energy-related issues needs to be dealt with on a much broader scale than design teams typically see. Energy is the amount of power consumed over a period of time to perform a given task, but reducing energy is a lot different than reducing power. It affects everything from operational costs and system performance to ... » read more

Adding Circuit Aging To Variability
By Brian Bailey - 12 Aug, 2021 - Comments: 0

Moving to a smaller node usually means another factor becomes important. The industry has become accustomed to doing process, temperature, voltage (PVT) corner analysis, but now it has to add aging into that mix. The problem is that planning for circuit aging is no longer a purely statistical process. Aging is dependent on activity over the lifetime of the device. Tools need to be modified a... » read more

10X Higher Productivity With VCS Dynamic Test Loading
By Synopsys - 11 Aug, 2021 - Comments: 0

The verification of a system-on-chip (SoC) is becoming increasingly complex, due to the multitude of functionality being implemented on a single chip. Different verification techniques are required at each level (IP, block, SoC and system) for faster verification closure. A successful verification strategy requires reuse of functional tests, faster test development and faster debug to improve t... » read more

Blog Review: Aug. 11
By Jesse Allen - 11 Aug, 2021 - Comments: 0

Arm's Rahul Mathur finds that traditional interconnects have become a bottleneck for improving IC performance and suggests buried interconnects as a way to lower signal routing delay. Cadence's Paul McLellan checks out forksheet FETs, a new transistor type that could allow scaling past 3nm, and the interconnect advances that will need to accompany it. A Synopsys writer explains the new LP... » read more

Designing Chips For Test Data
By Ed Sperling - 10 Aug, 2021 - Comments: 0

Collecting data to determine the health of a chip throughout its lifecycle is becoming necessary as chips are used in more critical applications, but being able to access that data isn't always so simple. It requires moving signals through a complex, sometimes unpredictable, and often hostile environment, which is a daunting challenge under the best of conditions. There is a growing sense of... » read more

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