Analog Fault Simulation


Anand Thiruvengadam, senior staff product marketing manager at Synopsys, drills down into the need for fault simulation in analog circuits in automotive designs. » read more

Blog Review: May 29


Cadence's Meera Collier traces the evolution of computing through the series of bottlenecks the industry has needed to overcome and what's being done to address the latest one. Mentor's Rebecca Lord checks out the use of differential signals to mitigate the effects of electromagnetic interference, noise, and crosstalk in PCBs. Synopsys' Taylor Armerding considers whether Ireland's slow en... » read more

Week in Review: IoT, Security, Auto


Internet of Things The Wing unit of Alphabet this summer will begin making drone deliveries in the Vuosarri district of Helsinki, Finland. The unmanned aerial vehicles will bear food and other items from Herkku Food, a gourmet market, and the Café Monami restaurant. The drones will bear deliveries of up to 3.3 pounds over distances of up to 6.2 miles. Comcast is reportedly developing an in... » read more

Week In Review: Design, Low Power


M&A Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera's revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between Globa... » read more

Blog Review: May 22


Synopsys' Taylor Armerding warns that critical infrastructure is still vulnerable to cyber threats, with Kaspersky finding that 42.7% of the industrial control system computers it protected last year were attacked by malware, email phishing, or other threats. Cadence's Paul McLellan listens in as Jon Masters of Red Hat considers how to tackle speculative execution and branch prediction vulne... » read more

In-Chip Monitoring Becoming Essential Below 10nm


Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

Week in Review: IoT, Security, Auto


Internet of Things Verizon Communications launched its nationwide narrowband Internet of Things network, saying it covers more than 92% of the U.S. population. “There is a whole universe of smart solutions needing scalable and affordable connections,” Jeffrey Dietel, senior vice president of business marketing and products, said in a statement. “By launching our NB-IoT network, Verizon i... » read more

Week In Review: Design, Low Power


Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

Blog Review: May 15


Cadence's Sean Dart shares an example of the kind of optimizations HLS tools can perform that would be difficult to find and implement by hand-coding RTL. Synopsys' Taylor Armerding takes a look at three cybersecurity initiatives from the U.S. government, from an IoT bill to improved voting machines, and whether they're likely to work. In a video, Mentor's Colin Walls points to why flashi... » read more

Chiplet Momentum Builds, Despite Tradeoffs


Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent 'chiplet' market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness. Chiplets provide an alternative mechanism for integrating intellectual property (IP) blocks into a semico... » read more

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